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cmd/asm,cmd/internal/obj/ppc64: add {l,st}xvx power9 instructions
These are the indexed vsx load operations with the
same endian and alignment benefits of {l,st}vx.
Likewise, cleanup redundant comments in op{load,store}x and
fix ISA 3.0 typos nearby.
Change-Id: Ie1ace17c6150cf9168a834e435114028ff6eb07c
Reviewed-on: https://go-review.googlesource.com/c/go/+/249025
Run-TryBot: Lynn Boger <laboger@linux.vnet.ibm.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: Lynn Boger <laboger@linux.vnet.ibm.com>
This commit is contained in:
Paul E. Murphy
Lynn Boger
parent
01aad9ea93
commit
64350f1eab
2
src/cmd/asm/internal/asm/testdata/ppc64.s
vendored
2
src/cmd/asm/internal/asm/testdata/ppc64.s
vendored
@ -1037,6 +1037,7 @@ label1:
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// VSX load with length X-form (also left-justified)
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LXVL R3,R4, VS0
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LXVLL R3,R4, VS0
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LXVX R3,R4, VS0
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// VSX load, DQ-form
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// <MNEMONIC> DQ(RA), XS produces
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// <mnemonic> XS, DQ(RA)
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@ -1060,6 +1061,7 @@ label1:
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// VSX store with length, X-form (also left-justified)
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STXVL VS0, R3,R4
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STXVLL VS0, R3,R4
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STXVX VS0, R3,R4
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// VSX move from VSR, XX1-form
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// <MNEMONIC> XS,RA produces
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2
src/cmd/asm/internal/asm/testdata/ppc64enc.s
vendored
2
src/cmd/asm/internal/asm/testdata/ppc64enc.s
vendored
@ -595,11 +595,13 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$0
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LXV 16(R3), VS1 // f4230011
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LXVL R3, R4, VS1 // 7c23221a
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LXVLL R3, R4, VS1 // 7c23225a
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LXVX R3, R4, VS1 // 7c232218
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LXSDX (R3)(R4), VS1 // 7c241c98
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STXVD2X VS1, (R3)(R4) // 7c241f98
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STXV VS1,16(R3) // f4230015
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STXVL VS1, R3, R4 // 7c23231a
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STXVLL VS1, R3, R4 // 7c23235a
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STXVX VS1, R3, R4 // 7c232318
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STXSDX VS1, (R3)(R4) // 7c241d98
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LXSIWAX (R3)(R4), VS1 // 7c241898
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STXSIWX VS1, (R3)(R4) // 7c241918
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@ -1584,8 +1584,9 @@ func buildop(ctxt *obj.Link) {
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case ALXV: /* lxv */
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opset(ALXV, r0)
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case ALXVL: /* lxvl */
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case ALXVL: /* lxvl, lxvll, lxvx */
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opset(ALXVLL, r0)
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opset(ALXVX, r0)
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case ASTXVD2X: /* stxvd2x, stxvdsx, stxvw4x, stxvh8x, stxvb16x */
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opset(ASTXVW4X, r0)
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@ -1595,8 +1596,9 @@ func buildop(ctxt *obj.Link) {
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case ASTXV: /* stxv */
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opset(ASTXV, r0)
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case ASTXVL: /* stxvl, stxvll */
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case ASTXVL: /* stxvl, stxvll, stvx */
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opset(ASTXVLL, r0)
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opset(ASTXVX, r0)
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case ALXSDX: /* lxsdx */
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opset(ALXSDX, r0)
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@ -5020,11 +5022,13 @@ func (c *ctxt9) opload(a obj.As) uint32 {
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case AMOVW:
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return OPVCC(58, 0, 0, 0) | 1<<1 /* lwa */
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case ALXV:
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return OPDQ(61, 1, 0) /* lxv - ISA v3.00 */
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return OPDQ(61, 1, 0) /* lxv - ISA v3.0 */
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case ALXVL:
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return OPVXX1(31, 269, 0) /* lxvl - ISA v3.00 */
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return OPVXX1(31, 269, 0) /* lxvl - ISA v3.0 */
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case ALXVLL:
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return OPVXX1(31, 301, 0) /* lxvll - ISA v3.00 */
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return OPVXX1(31, 301, 0) /* lxvll - ISA v3.0 */
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case ALXVX:
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return OPVXX1(31, 268, 0) /* lxvx - ISA v3.0 */
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/* no AMOVWU */
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case AMOVB, AMOVBZ:
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@ -5122,8 +5126,6 @@ func (c *ctxt9) oploadx(a obj.As) uint32 {
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return OPVCC(31, 309, 0, 0) /* ldmx */
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/* Vector (VMX/Altivec) instructions */
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/* ISA 2.03 enables these for PPC970. For POWERx processors, these */
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/* are enabled starting at POWER6 (ISA 2.05). */
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case ALVEBX:
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return OPVCC(31, 7, 0, 0) /* lvebx - v2.03 */
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case ALVEHX:
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@ -5141,7 +5143,8 @@ func (c *ctxt9) oploadx(a obj.As) uint32 {
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/* End of vector instructions */
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/* Vector scalar (VSX) instructions */
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/* ISA 2.06 enables these for POWER7. */
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case ALXVX:
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return OPVXX1(31, 268, 0) /* lxvx - ISA v3.0 */
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case ALXVD2X:
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return OPVXX1(31, 844, 0) /* lxvd2x - v2.06 */
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case ALXVW4X:
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@ -5208,6 +5211,8 @@ func (c *ctxt9) opstore(a obj.As) uint32 {
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return OPVXX1(31, 397, 0) /* stxvl ISA 3.0 */
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case ASTXVLL:
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return OPVXX1(31, 429, 0) /* stxvll ISA 3.0 */
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case ASTXVX:
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return OPVXX1(31, 396, 0) /* stxvx - ISA v3.0 */
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}
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@ -5271,8 +5276,6 @@ func (c *ctxt9) opstorex(a obj.As) uint32 {
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return OPVCC(31, 181, 0, 0) /* stdux */
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/* Vector (VMX/Altivec) instructions */
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/* ISA 2.03 enables these for PPC970. For POWERx processors, these */
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/* are enabled starting at POWER6 (ISA 2.05). */
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case ASTVEBX:
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return OPVCC(31, 135, 0, 0) /* stvebx - v2.03 */
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case ASTVEHX:
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@ -5286,15 +5289,16 @@ func (c *ctxt9) opstorex(a obj.As) uint32 {
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/* End of vector instructions */
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/* Vector scalar (VSX) instructions */
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/* ISA 2.06 enables these for POWER7. */
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case ASTXVX:
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return OPVXX1(31, 396, 0) /* stxvx - v3.0 */
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case ASTXVD2X:
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return OPVXX1(31, 972, 0) /* stxvd2x - v2.06 */
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case ASTXVW4X:
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return OPVXX1(31, 908, 0) /* stxvw4x - v2.06 */
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case ASTXVH8X:
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return OPVXX1(31, 940, 0) /* stxvh8x - v3.00 */
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return OPVXX1(31, 940, 0) /* stxvh8x - v3.0 */
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case ASTXVB16X:
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return OPVXX1(31, 1004, 0) /* stxvb16x - v3.00 */
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return OPVXX1(31, 1004, 0) /* stxvb16x - v3.0 */
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case ASTXSDX:
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return OPVXX1(31, 716, 0) /* stxsdx - v2.06 */
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