From 5e31f78c8a4ed1b872ddc194f0cd1ae931b37d7e Mon Sep 17 00:00:00 2001
From: Meng Zhuo <mzh@golangcn.org>
Date: Fri, 8 Sep 2023 17:53:34 +0800
Subject: [PATCH] internal/cpu: fix wrong cache line size of riscv64

All of riscv CPU using 64B for cache-line size.
i.e. U540 of Hifive Unleashed (https://www.sifive.com/boards/hifive-unleashed)

Change-Id: I0d72d88ac026f45383c3b3eb3a77233d3c2e4004
Reviewed-on: https://go-review.googlesource.com/c/go/+/526659
Run-TryBot: M Zhuo <mzh@golangcn.org>
Reviewed-by: Cherry Mui <cherryyz@google.com>
Reviewed-by: Heschi Kreinick <heschi@google.com>
TryBot-Result: Gopher Robot <gobot@golang.org>
---
 src/internal/cpu/cpu_riscv64.go | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/internal/cpu/cpu_riscv64.go b/src/internal/cpu/cpu_riscv64.go
index 54b8c3378b4..2173fe88860 100644
--- a/src/internal/cpu/cpu_riscv64.go
+++ b/src/internal/cpu/cpu_riscv64.go
@@ -4,7 +4,7 @@
 
 package cpu
 
-const CacheLinePadSize = 32
+const CacheLinePadSize = 64
 
 func doinit() {
 }