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https://github.com/golang/go
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cmd/internal/obj/ppc64: rework argument classifications
This introduces a number of new classifications which will make it easier to generate functions to assemble the new instructions of ISA 3.1, and potentially earlier versions. No code generation changes should occur as a result of these. These allow finer control over how an opcode is matched to an optab entry. Literal values are now classified based on the smallest number of bits needed to encode, and matching rules will accept a literal if it can be zero/sign extended to fit a larger literal class. Likewise, support classifying even register numbers for GPR, VSX, and FPR instructions. Some instructions require and even/odd register pair, and these are usually represented by specifying the even register, and similarly encoded. Likewise, add a unit test for the argument classifier function (aclass). This caught an off-by-one bug in aclass which is also fixed. Updates #44549 Change-Id: Ia03013aea8b56c4d59b7c3812cdd67ddb3b720b9 Reviewed-on: https://go-review.googlesource.com/c/go/+/350152 Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Lynn Boger <laboger@linux.vnet.ibm.com> Run-TryBot: Cherry Mui <cherryyz@google.com> TryBot-Result: Go Bot <gobot@golang.org>
This commit is contained in:
Paul E. Murphy
Lynn Boger
parent
b8da7e4c4c
commit
5a3d0f5a63
@ -351,40 +351,63 @@ const (
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const (
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C_NONE = iota
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C_REG
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C_FREG
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C_VREG
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C_VSREG
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C_CREG
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C_REGP /* An even numbered gpr which can be used a gpr pair argument */
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C_REG /* Any gpr register */
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C_FREGP /* An even numbered fpr which can be used a fpr pair argument */
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C_FREG /* Any fpr register */
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C_VREG /* Any vector register */
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C_VSREGP /* An even numbered vsx register which can be used as a vsx register pair argument */
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C_VSREG /* Any vector-scalar register */
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C_CREG /* The condition registor (CR) or a condition register field (CRx) */
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C_SPR /* special processor register */
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C_ZCON
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C_SCON /* 16 bit signed */
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C_UCON /* 32 bit signed, low 16 bits 0 */
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C_ADDCON /* -0x8000 <= v < 0 */
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C_ANDCON /* 0 < v <= 0xFFFF */
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C_LCON /* other 32 */
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C_DCON /* other 64 (could subdivide further) */
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C_ZCON /* The constant zero */
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C_U1CON /* 1 bit unsigned constant */
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C_U2CON /* 2 bit unsigned constant */
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C_U3CON /* 3 bit unsigned constant */
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C_U4CON /* 4 bit unsigned constant */
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C_U5CON /* 5 bit unsigned constant */
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C_U8CON /* 8 bit unsigned constant */
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C_U15CON /* 15 bit unsigned constant */
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C_S16CON /* 16 bit signed constant */
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C_U16CON /* 16 bit unsigned constant */
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C_32S16CON /* Any 32 bit constant of the form 0x....0000, signed or unsigned */
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C_32CON /* Any constant which fits into 32 bits. Can be signed or unsigned */
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C_S34CON /* 34 bit signed constant */
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C_64CON /* Any constant which fits into 64 bits. Can be signed or unsigned */
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C_SACON /* $n(REG) where n <= int16 */
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C_LACON /* $n(REG) where int16 < n <= int32 */
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C_DACON /* $n(REG) where int32 < n */
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C_SBRA
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C_LBRA
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C_LBRAPIC
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C_ZOREG // conjecture: either (1) register + zeroed offset, or (2) "R0" implies zero or C_REG
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C_SOREG // D/DS form memory operation
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C_LOREG // 32 bit addis + D/DS-form memory operation
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C_FPSCR
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C_XER
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C_LR
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C_CTR
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C_ANY
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C_GOK
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C_ADDR
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C_TLS_LE
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C_TLS_IE
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C_TEXTSIZE
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C_LACON /* $n(REG) where n <= int32 */
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C_DACON /* $n(REG) where n <= int64 */
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C_SBRA /* A short offset argument to a branching instruction */
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C_LBRA /* A long offset argument to a branching instruction */
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C_LBRAPIC /* Like C_LBRA, but requires an extra NOP for potential TOC restore by the linker. */
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C_ZOREG /* An reg+reg memory arg, or a $0+reg memory op */
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C_SOREG /* An $n+reg memory arg where n is a 16 bit signed offset */
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C_LOREG /* An $n+reg memory arg where n is a 32 bit signed offset */
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C_FPSCR /* The fpscr register */
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C_XER /* The xer, holds the carry bit */
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C_LR /* The link register */
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C_CTR /* The count register */
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C_ANY /* Any argument */
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C_GOK /* A non-matched argument */
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C_ADDR /* A symbolic memory location */
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C_TLS_LE /* A thread local, local-exec, type memory arg */
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C_TLS_IE /* A thread local, initial-exec, type memory arg */
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C_TEXTSIZE /* An argument with Type obj.TYPE_TEXTSIZE */
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C_NCLASS /* must be the last */
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/* Aliased names which should be cleaned up, or integrated. */
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C_SCON = C_U15CON
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C_UCON = C_32S16CON
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C_ADDCON = C_S16CON
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C_ANDCON = C_U16CON
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C_LCON = C_32CON
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/* Aliased names which may be generated by ppc64map for the optab. */
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C_S3216CON = C_32S16CON // TODO: these should be treated differently (e.g xoris vs addis)
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C_U3216CON = C_32S16CON
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C_S32CON = C_32CON
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C_U32CON = C_32CON
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)
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const (
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@ -6,19 +6,29 @@ package ppc64
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var cnames9 = []string{
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"NONE",
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"REGP",
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"REG",
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"FREGP",
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"FREG",
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"VREG",
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"VSREGP",
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"VSREG",
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"CREG",
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"SPR",
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"ZCON",
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"SCON",
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"UCON",
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"ADDCON",
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"ANDCON",
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"LCON",
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"DCON",
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"U1CON",
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"U2CON",
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"U3CON",
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"U4CON",
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"U5CON",
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"U8CON",
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"U15CON",
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"S16CON",
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"U16CON",
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"32S16CON",
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"32CON",
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"S34CON",
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"64CON",
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"SACON",
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"LACON",
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"DACON",
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@ -307,8 +307,7 @@ var optab = []Optab{
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{as: ABC, a6: C_ZOREG, type_: 15, size: 8},
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{as: ASYNC, type_: 46, size: 4},
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{as: AWORD, a1: C_LCON, type_: 40, size: 4},
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{as: ADWORD, a1: C_LCON, type_: 31, size: 8},
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{as: ADWORD, a1: C_DCON, type_: 31, size: 8},
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{as: ADWORD, a1: C_64CON, type_: 31, size: 8},
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{as: ADWORD, a1: C_LACON, type_: 31, size: 8},
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{as: AADDME, a1: C_REG, a6: C_REG, type_: 47, size: 4},
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{as: AEXTSB, a1: C_REG, a6: C_REG, type_: 48, size: 4},
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@ -336,7 +335,7 @@ var optab = []Optab{
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{as: ALDMX, a1: C_SOREG, a6: C_REG, type_: 45, size: 4}, /* load doubleword monitored, x-form */
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{as: AMADDHD, a1: C_REG, a2: C_REG, a3: C_REG, a6: C_REG, type_: 83, size: 4}, /* multiply-add high/low doubleword, va-form */
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{as: AADDEX, a1: C_REG, a2: C_REG, a3: C_SCON, a6: C_REG, type_: 94, size: 4}, /* add extended using alternate carry, z23-form */
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{as: ACRAND, a1: C_CREG, a6: C_CREG, type_: 2, size: 4}, /* logical ops for condition registers xl-form */
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{as: ACRAND, a1: C_CREG, a2: C_CREG, a6: C_CREG, type_: 2, size: 4}, /* logical ops for condition register bits xl-form */
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/* Vector instructions */
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@ -485,15 +484,15 @@ var optab = []Optab{
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{as: AXVCVSXDDP, a1: C_VSREG, a6: C_VSREG, type_: 89, size: 4}, /* vsx vector integer-fp conversion, xx2-form */
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{as: ACMP, a1: C_REG, a6: C_REG, type_: 70, size: 4},
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{as: ACMP, a1: C_REG, a2: C_REG, a6: C_REG, type_: 70, size: 4},
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{as: ACMP, a1: C_REG, a2: C_CREG, a6: C_REG, type_: 70, size: 4},
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{as: ACMP, a1: C_REG, a6: C_ADDCON, type_: 71, size: 4},
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{as: ACMP, a1: C_REG, a2: C_REG, a6: C_ADDCON, type_: 71, size: 4},
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{as: ACMP, a1: C_REG, a2: C_CREG, a6: C_ADDCON, type_: 71, size: 4},
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{as: ACMPU, a1: C_REG, a6: C_REG, type_: 70, size: 4},
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{as: ACMPU, a1: C_REG, a2: C_REG, a6: C_REG, type_: 70, size: 4},
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{as: ACMPU, a1: C_REG, a2: C_CREG, a6: C_REG, type_: 70, size: 4},
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{as: ACMPU, a1: C_REG, a6: C_ANDCON, type_: 71, size: 4},
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{as: ACMPU, a1: C_REG, a2: C_REG, a6: C_ANDCON, type_: 71, size: 4},
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{as: ACMPU, a1: C_REG, a2: C_CREG, a6: C_ANDCON, type_: 71, size: 4},
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{as: AFCMPO, a1: C_FREG, a6: C_FREG, type_: 70, size: 4},
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{as: AFCMPO, a1: C_FREG, a2: C_REG, a6: C_FREG, type_: 70, size: 4},
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{as: AFCMPO, a1: C_FREG, a2: C_CREG, a6: C_FREG, type_: 70, size: 4},
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{as: ATW, a1: C_LCON, a2: C_REG, a6: C_REG, type_: 60, size: 4},
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{as: ATW, a1: C_LCON, a2: C_REG, a6: C_ADDCON, type_: 61, size: 4},
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{as: ADCBF, a1: C_ZOREG, type_: 43, size: 4},
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@ -584,9 +583,11 @@ func addpad(pc, a int64, ctxt *obj.Link, cursym *obj.LSym) int {
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// or "MOVD R5, foo+10(SP) or pseudo-register is used. The other common case is when
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// generating constants in register like "MOVD $constant, Rx".
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func (c *ctxt9) getimpliedreg(a *obj.Addr, p *obj.Prog) int {
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switch oclass(a) {
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case C_ADDCON, C_ANDCON, C_UCON, C_LCON, C_SCON, C_ZCON:
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class := oclass(a)
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if class >= C_ZCON && class <= C_64CON {
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return REGZERO
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}
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switch class {
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case C_SACON, C_LACON:
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return REGSP
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case C_LOREG, C_SOREG, C_ZOREG:
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@ -839,29 +840,24 @@ func isuint32(v uint64) bool {
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return uint64(uint32(v)) == v
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}
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func (c *ctxt9) aclass(a *obj.Addr) int {
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switch a.Type {
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case obj.TYPE_NONE:
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return C_NONE
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case obj.TYPE_REG:
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if REG_R0 <= a.Reg && a.Reg <= REG_R31 {
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return C_REG
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func (c *ctxt9) aclassreg(reg int16) int {
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if REG_R0 <= reg && reg <= REG_R31 {
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return C_REGP + int(reg&1)
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}
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if REG_F0 <= a.Reg && a.Reg <= REG_F31 {
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return C_FREG
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if REG_F0 <= reg && reg <= REG_F31 {
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return C_FREGP + int(reg&1)
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}
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if REG_V0 <= a.Reg && a.Reg <= REG_V31 {
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if REG_V0 <= reg && reg <= REG_V31 {
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return C_VREG
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}
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if REG_VS0 <= a.Reg && a.Reg <= REG_VS63 {
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return C_VSREG
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if REG_VS0 <= reg && reg <= REG_VS63 {
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return C_VSREGP + int(reg&1)
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}
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if REG_CR0 <= a.Reg && a.Reg <= REG_CR7 || a.Reg == REG_CR {
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if REG_CR0 <= reg && reg <= REG_CR7 || reg == REG_CR {
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return C_CREG
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}
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if REG_SPR0 <= a.Reg && a.Reg <= REG_SPR0+1023 {
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switch a.Reg {
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if REG_SPR0 <= reg && reg <= REG_SPR0+1023 {
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switch reg {
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case REG_LR:
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return C_LR
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@ -874,10 +870,19 @@ func (c *ctxt9) aclass(a *obj.Addr) int {
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return C_SPR
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}
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if a.Reg == REG_FPSCR {
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if reg == REG_FPSCR {
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return C_FPSCR
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}
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return C_GOK
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}
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func (c *ctxt9) aclass(a *obj.Addr) int {
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switch a.Type {
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case obj.TYPE_NONE:
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return C_NONE
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case obj.TYPE_REG:
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return c.aclassreg(a.Reg)
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case obj.TYPE_MEM:
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switch a.Name {
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@ -948,7 +953,7 @@ func (c *ctxt9) aclass(a *obj.Addr) int {
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case obj.NAME_NONE:
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c.instoffset = a.Offset
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if a.Reg != 0 {
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if -BIG <= c.instoffset && c.instoffset <= BIG {
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if -BIG <= c.instoffset && c.instoffset < BIG {
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return C_SACON
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}
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if isint32(c.instoffset) {
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@ -985,34 +990,46 @@ func (c *ctxt9) aclass(a *obj.Addr) int {
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}
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if c.instoffset >= 0 {
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if c.instoffset == 0 {
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return C_ZCON
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sbits := bits.Len64(uint64(c.instoffset))
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switch {
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case sbits <= 5:
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return C_ZCON + sbits
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case sbits <= 8:
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return C_U8CON
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case sbits <= 15:
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return C_U15CON
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case sbits <= 16:
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return C_U16CON
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case sbits <= 31:
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// Special case, a positive int32 value which is a multiple of 2^16
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if c.instoffset&0xFFFF == 0 {
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return C_U3216CON
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}
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if c.instoffset <= 0x7fff {
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return C_SCON
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return C_U32CON
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case sbits <= 32:
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return C_U32CON
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case sbits <= 33:
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return C_S34CON
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default:
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return C_64CON
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}
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if c.instoffset <= 0xffff {
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return C_ANDCON
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} else {
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sbits := bits.Len64(uint64(^c.instoffset))
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switch {
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case sbits <= 15:
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return C_S16CON
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case sbits <= 31:
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// Special case, a negative int32 value which is a multiple of 2^16
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if c.instoffset&0xFFFF == 0 {
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return C_S3216CON
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}
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if c.instoffset&0xffff == 0 && isuint32(uint64(c.instoffset)) { /* && (instoffset & (1<<31)) == 0) */
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return C_UCON
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return C_S32CON
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case sbits <= 33:
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return C_S34CON
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default:
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return C_64CON
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}
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if isint32(c.instoffset) || isuint32(uint64(c.instoffset)) {
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return C_LCON
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}
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return C_DCON
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}
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if c.instoffset >= -0x8000 {
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return C_ADDCON
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}
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if c.instoffset&0xffff == 0 && isint32(c.instoffset) {
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return C_UCON
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}
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if isint32(c.instoffset) {
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return C_LCON
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}
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return C_DCON
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case obj.TYPE_BRANCH:
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if a.Sym != nil && c.ctxt.Flag_dynlink {
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@ -1062,15 +1079,7 @@ func (c *ctxt9) oplook(p *obj.Prog) *Optab {
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a2 := C_NONE
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if p.Reg != 0 {
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if REG_R0 <= p.Reg && p.Reg <= REG_R31 {
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a2 = C_REG
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} else if REG_V0 <= p.Reg && p.Reg <= REG_V31 {
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a2 = C_VREG
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} else if REG_VS0 <= p.Reg && p.Reg <= REG_VS63 {
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a2 = C_VSREG
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} else if REG_F0 <= p.Reg && p.Reg <= REG_F31 {
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a2 = C_FREG
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}
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a2 = c.aclassreg(p.Reg)
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}
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// c.ctxt.Logf("oplook %v %d %d %d %d\n", p, a1, a2, a3, a4, a5, a6)
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@ -1097,71 +1106,72 @@ func (c *ctxt9) oplook(p *obj.Prog) *Optab {
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return &ops[0]
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}
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// Compare two operand types (ex C_REG, or C_SCON)
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// and return true if b is compatible with a.
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//
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// Argument comparison isn't reflexitive, so care must be taken.
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// a is the argument type as found in optab, b is the argument as
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// fitted by aclass.
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func cmp(a int, b int) bool {
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if a == b {
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return true
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}
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switch a {
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case C_LCON:
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if b == C_ZCON || b == C_SCON || b == C_UCON || b == C_ADDCON || b == C_ANDCON {
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return true
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}
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case C_ADDCON:
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if b == C_ZCON || b == C_SCON {
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return true
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}
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case C_ANDCON:
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if b == C_ZCON || b == C_SCON {
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return true
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}
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case C_SPR:
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if b == C_LR || b == C_XER || b == C_CTR {
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return true
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}
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case C_UCON:
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if b == C_ZCON {
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return true
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}
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case C_U1CON:
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return cmp(C_ZCON, b)
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case C_U2CON:
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return cmp(C_U1CON, b)
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case C_U3CON:
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return cmp(C_U2CON, b)
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case C_U4CON:
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return cmp(C_U3CON, b)
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||||
case C_U5CON:
|
||||
return cmp(C_U4CON, b)
|
||||
case C_U8CON:
|
||||
return cmp(C_U5CON, b)
|
||||
case C_U15CON:
|
||||
return cmp(C_U8CON, b)
|
||||
case C_U16CON:
|
||||
return cmp(C_U15CON, b)
|
||||
|
||||
case C_SCON:
|
||||
if b == C_ZCON {
|
||||
return true
|
||||
}
|
||||
case C_S16CON:
|
||||
return cmp(C_U15CON, b)
|
||||
case C_32CON:
|
||||
return cmp(C_S16CON, b) || cmp(C_U16CON, b) || cmp(C_32S16CON, b)
|
||||
case C_S34CON:
|
||||
return cmp(C_32CON, b)
|
||||
case C_64CON:
|
||||
return cmp(C_S34CON, b)
|
||||
|
||||
case C_32S16CON:
|
||||
return cmp(C_ZCON, b)
|
||||
|
||||
case C_LACON:
|
||||
if b == C_SACON {
|
||||
return true
|
||||
}
|
||||
return cmp(C_SACON, b)
|
||||
|
||||
case C_LBRA:
|
||||
if b == C_SBRA {
|
||||
return true
|
||||
}
|
||||
return cmp(C_SBRA, b)
|
||||
|
||||
case C_SOREG:
|
||||
if b == C_ZOREG {
|
||||
return true
|
||||
}
|
||||
return cmp(C_ZOREG, b)
|
||||
|
||||
case C_LOREG:
|
||||
if b == C_SOREG || b == C_ZOREG {
|
||||
return true
|
||||
}
|
||||
return cmp(C_SOREG, b)
|
||||
|
||||
// An even/odd register input always matches the regular register types.
|
||||
case C_REG:
|
||||
if b == C_ZCON {
|
||||
return r0iszero != 0 /*TypeKind(100016)*/
|
||||
}
|
||||
|
||||
return cmp(C_REGP, b) || (b == C_ZCON && r0iszero != 0)
|
||||
case C_FREG:
|
||||
return cmp(C_FREGP, b)
|
||||
case C_VSREG:
|
||||
/* Allow any VR argument as a VSR operand. */
|
||||
if b == C_VREG {
|
||||
return true
|
||||
}
|
||||
return cmp(C_VSREGP, b) || cmp(C_VREG, b)
|
||||
|
||||
case C_ANY:
|
||||
return true
|
||||
|
||||
@ -6,9 +6,12 @@ package ppc64
|
||||
|
||||
import (
|
||||
"bytes"
|
||||
"cmd/internal/obj"
|
||||
"cmd/internal/objabi"
|
||||
"fmt"
|
||||
"internal/testenv"
|
||||
"io/ioutil"
|
||||
"math"
|
||||
"os"
|
||||
"os/exec"
|
||||
"path/filepath"
|
||||
@ -437,3 +440,114 @@ func TestRegValueAlignment(t *testing.T) {
|
||||
tstFunc(t.rstart, t.rend, t.msk, t.rout)
|
||||
}
|
||||
}
|
||||
|
||||
// Verify interesting obj.Addr arguments are classified correctly.
|
||||
func TestAddrClassifier(t *testing.T) {
|
||||
type cmplx struct {
|
||||
pic int
|
||||
pic_dyn int
|
||||
dyn int
|
||||
nonpic int
|
||||
}
|
||||
tsts := [...]struct {
|
||||
arg obj.Addr
|
||||
output interface{}
|
||||
}{
|
||||
// Supported register type args
|
||||
{obj.Addr{Type: obj.TYPE_REG, Reg: REG_R1}, C_REG},
|
||||
{obj.Addr{Type: obj.TYPE_REG, Reg: REG_R2}, C_REGP},
|
||||
{obj.Addr{Type: obj.TYPE_REG, Reg: REG_F1}, C_FREG},
|
||||
{obj.Addr{Type: obj.TYPE_REG, Reg: REG_F2}, C_FREGP},
|
||||
{obj.Addr{Type: obj.TYPE_REG, Reg: REG_V2}, C_VREG},
|
||||
{obj.Addr{Type: obj.TYPE_REG, Reg: REG_VS1}, C_VSREG},
|
||||
{obj.Addr{Type: obj.TYPE_REG, Reg: REG_VS2}, C_VSREGP},
|
||||
{obj.Addr{Type: obj.TYPE_REG, Reg: REG_CR}, C_CREG},
|
||||
{obj.Addr{Type: obj.TYPE_REG, Reg: REG_CR1}, C_CREG},
|
||||
{obj.Addr{Type: obj.TYPE_REG, Reg: REG_SPR0}, C_SPR},
|
||||
{obj.Addr{Type: obj.TYPE_REG, Reg: REG_SPR0 + 1}, C_XER},
|
||||
{obj.Addr{Type: obj.TYPE_REG, Reg: REG_SPR0 + 8}, C_LR},
|
||||
{obj.Addr{Type: obj.TYPE_REG, Reg: REG_SPR0 + 9}, C_CTR},
|
||||
{obj.Addr{Type: obj.TYPE_REG, Reg: REG_FPSCR}, C_FPSCR},
|
||||
|
||||
// Memory type arguments.
|
||||
{obj.Addr{Type: obj.TYPE_MEM, Name: obj.NAME_GOTREF}, C_ADDR},
|
||||
{obj.Addr{Type: obj.TYPE_MEM, Name: obj.NAME_TOCREF}, C_ADDR},
|
||||
{obj.Addr{Type: obj.TYPE_MEM, Name: obj.NAME_EXTERN, Sym: &obj.LSym{Type: objabi.STLSBSS}}, cmplx{C_TLS_IE, C_TLS_IE, C_TLS_LE, C_TLS_LE}},
|
||||
{obj.Addr{Type: obj.TYPE_MEM, Name: obj.NAME_EXTERN, Sym: &obj.LSym{Type: objabi.SDATA}}, C_ADDR},
|
||||
{obj.Addr{Type: obj.TYPE_MEM, Name: obj.NAME_AUTO}, C_SOREG},
|
||||
{obj.Addr{Type: obj.TYPE_MEM, Name: obj.NAME_AUTO, Offset: BIG}, C_LOREG},
|
||||
{obj.Addr{Type: obj.TYPE_MEM, Name: obj.NAME_AUTO, Offset: -BIG - 1}, C_LOREG},
|
||||
{obj.Addr{Type: obj.TYPE_MEM, Name: obj.NAME_PARAM}, C_SOREG},
|
||||
{obj.Addr{Type: obj.TYPE_MEM, Name: obj.NAME_PARAM, Offset: BIG}, C_LOREG},
|
||||
{obj.Addr{Type: obj.TYPE_MEM, Name: obj.NAME_PARAM, Offset: -BIG - 33}, C_LOREG}, // 33 is FixedFrameSize-1
|
||||
{obj.Addr{Type: obj.TYPE_MEM, Name: obj.NAME_NONE}, C_ZOREG},
|
||||
{obj.Addr{Type: obj.TYPE_MEM, Name: obj.NAME_NONE, Offset: 1}, C_SOREG},
|
||||
{obj.Addr{Type: obj.TYPE_MEM, Name: obj.NAME_NONE, Offset: BIG}, C_LOREG},
|
||||
{obj.Addr{Type: obj.TYPE_MEM, Name: obj.NAME_NONE, Offset: -BIG - 33}, C_LOREG},
|
||||
|
||||
// Misc (golang initializes -0.0 to 0.0, hence the obfuscation below)
|
||||
{obj.Addr{Type: obj.TYPE_TEXTSIZE}, C_TEXTSIZE},
|
||||
{obj.Addr{Type: obj.TYPE_FCONST, Val: 0.0}, C_ZCON},
|
||||
{obj.Addr{Type: obj.TYPE_FCONST, Val: math.Float64frombits(0x8000000000000000)}, C_S16CON},
|
||||
|
||||
// Address type arguments
|
||||
{obj.Addr{Type: obj.TYPE_ADDR, Reg: REG_R0, Name: obj.NAME_NONE, Offset: 1}, C_SACON},
|
||||
{obj.Addr{Type: obj.TYPE_ADDR, Reg: REG_R0, Name: obj.NAME_NONE, Offset: BIG}, C_LACON},
|
||||
{obj.Addr{Type: obj.TYPE_ADDR, Reg: REG_R0, Name: obj.NAME_NONE, Offset: -BIG - 1}, C_LACON},
|
||||
{obj.Addr{Type: obj.TYPE_ADDR, Reg: REG_R0, Name: obj.NAME_NONE, Offset: 1 << 32}, C_DACON},
|
||||
{obj.Addr{Type: obj.TYPE_ADDR, Name: obj.NAME_EXTERN, Sym: &obj.LSym{Type: objabi.SDATA}}, C_LACON},
|
||||
{obj.Addr{Type: obj.TYPE_ADDR, Name: obj.NAME_STATIC, Sym: &obj.LSym{Type: objabi.SDATA}}, C_LACON},
|
||||
{obj.Addr{Type: obj.TYPE_ADDR, Reg: REG_R0, Name: obj.NAME_AUTO, Offset: 1}, C_SACON},
|
||||
{obj.Addr{Type: obj.TYPE_ADDR, Reg: REG_R0, Name: obj.NAME_AUTO, Offset: BIG}, C_LACON},
|
||||
{obj.Addr{Type: obj.TYPE_ADDR, Reg: REG_R0, Name: obj.NAME_AUTO, Offset: -BIG - 1}, C_LACON},
|
||||
{obj.Addr{Type: obj.TYPE_ADDR, Reg: REG_R0, Name: obj.NAME_PARAM, Offset: 1}, C_SACON},
|
||||
{obj.Addr{Type: obj.TYPE_ADDR, Reg: REG_R0, Name: obj.NAME_PARAM, Offset: BIG}, C_LACON},
|
||||
{obj.Addr{Type: obj.TYPE_ADDR, Reg: REG_R0, Name: obj.NAME_PARAM, Offset: -BIG - 33}, C_LACON}, // 33 is FixedFrameSize-1
|
||||
|
||||
// Constant type arguments
|
||||
{obj.Addr{Type: obj.TYPE_CONST, Name: obj.NAME_NONE, Offset: 0}, C_ZCON},
|
||||
{obj.Addr{Type: obj.TYPE_CONST, Name: obj.NAME_NONE, Offset: 1}, C_U1CON},
|
||||
{obj.Addr{Type: obj.TYPE_CONST, Name: obj.NAME_NONE, Offset: 2}, C_U2CON},
|
||||
{obj.Addr{Type: obj.TYPE_CONST, Name: obj.NAME_NONE, Offset: 4}, C_U3CON},
|
||||
{obj.Addr{Type: obj.TYPE_CONST, Name: obj.NAME_NONE, Offset: 8}, C_U4CON},
|
||||
{obj.Addr{Type: obj.TYPE_CONST, Name: obj.NAME_NONE, Offset: 16}, C_U5CON},
|
||||
{obj.Addr{Type: obj.TYPE_CONST, Name: obj.NAME_NONE, Offset: 32}, C_U8CON},
|
||||
{obj.Addr{Type: obj.TYPE_CONST, Name: obj.NAME_NONE, Offset: 1 << 14}, C_U15CON},
|
||||
{obj.Addr{Type: obj.TYPE_CONST, Name: obj.NAME_NONE, Offset: 1 << 15}, C_U16CON},
|
||||
{obj.Addr{Type: obj.TYPE_CONST, Name: obj.NAME_NONE, Offset: 1 << 16}, C_U3216CON},
|
||||
{obj.Addr{Type: obj.TYPE_CONST, Name: obj.NAME_NONE, Offset: 1 + 1<<16}, C_U32CON},
|
||||
{obj.Addr{Type: obj.TYPE_CONST, Name: obj.NAME_NONE, Offset: 1 << 32}, C_S34CON},
|
||||
{obj.Addr{Type: obj.TYPE_CONST, Name: obj.NAME_NONE, Offset: 1 << 33}, C_64CON},
|
||||
{obj.Addr{Type: obj.TYPE_CONST, Name: obj.NAME_NONE, Offset: -1}, C_S16CON},
|
||||
{obj.Addr{Type: obj.TYPE_CONST, Name: obj.NAME_NONE, Offset: -0x10000}, C_S3216CON},
|
||||
{obj.Addr{Type: obj.TYPE_CONST, Name: obj.NAME_NONE, Offset: -0x10001}, C_S32CON},
|
||||
{obj.Addr{Type: obj.TYPE_CONST, Name: obj.NAME_NONE, Offset: -(1 << 33)}, C_S34CON},
|
||||
{obj.Addr{Type: obj.TYPE_CONST, Name: obj.NAME_NONE, Offset: -(1 << 34)}, C_64CON},
|
||||
|
||||
// Branch like arguments
|
||||
{obj.Addr{Type: obj.TYPE_BRANCH, Sym: &obj.LSym{Type: objabi.SDATA}}, cmplx{C_SBRA, C_LBRAPIC, C_LBRAPIC, C_SBRA}},
|
||||
{obj.Addr{Type: obj.TYPE_BRANCH}, C_SBRA},
|
||||
}
|
||||
|
||||
pic_ctxt9 := ctxt9{ctxt: &obj.Link{Flag_shared: true, Arch: &Linkppc64}, autosize: 0}
|
||||
pic_dyn_ctxt9 := ctxt9{ctxt: &obj.Link{Flag_shared: true, Flag_dynlink: true, Arch: &Linkppc64}, autosize: 0}
|
||||
dyn_ctxt9 := ctxt9{ctxt: &obj.Link{Flag_dynlink: true, Arch: &Linkppc64}, autosize: 0}
|
||||
nonpic_ctxt9 := ctxt9{ctxt: &obj.Link{Arch: &Linkppc64}, autosize: 0}
|
||||
ctxts := [...]*ctxt9{&pic_ctxt9, &pic_dyn_ctxt9, &dyn_ctxt9, &nonpic_ctxt9}
|
||||
name := [...]string{"pic", "pic_dyn", "dyn", "nonpic"}
|
||||
for _, tst := range tsts {
|
||||
var expect []int
|
||||
switch tst.output.(type) {
|
||||
case cmplx:
|
||||
v := tst.output.(cmplx)
|
||||
expect = []int{v.pic, v.pic_dyn, v.dyn, v.nonpic}
|
||||
case int:
|
||||
expect = []int{tst.output.(int), tst.output.(int), tst.output.(int), tst.output.(int)}
|
||||
}
|
||||
for i, _ := range ctxts {
|
||||
if output := ctxts[i].aclass(&tst.arg); output != expect[i] {
|
||||
t.Errorf("%s.aclass(%v) = %v, expected %v\n", name[i], tst.arg, DRconv(output), DRconv(expect[i]))
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user