From 56b62c7cf0268eefc0d909e8e8351c4ff6a62148 Mon Sep 17 00:00:00 2001 From: Wei Xiao Date: Tue, 18 Jul 2017 12:25:37 +0800 Subject: [PATCH] cmd/vendor/golang.org/x/arch: pull updates from x repo Vendor from golang.org/x/arch (commit f185940). Implements #19157 Updates #12840 Updates #20762 Updates #20897 Updates #20096 Updates #20766 Updates #20752 Updates #20096 Updates #19142 Change-Id: Idefb8ba2c355dc07f3b9e8dcf5f00173256a0f0f Reviewed-on: https://go-review.googlesource.com/49530 Reviewed-by: Cherry Zhang --- .../golang.org/x/arch/arm/armasm/decode.go | 8 +- .../golang.org/x/arch/arm/armasm/plan9x.go | 77 +- .../golang.org/x/arch/arm/armasm/tables.go | 104 + .../x/arch/arm/armasm/testdata/decode.txt | 1250 +++ .../golang.org/x/arch/arm64/arm64asm/arg.go | 494 + .../x/arch/arm64/arm64asm/condition.go | 329 + .../x/arch/arm64/arm64asm/condition_util.go | 81 + .../x/arch/arm64/arm64asm/decode.go | 2768 +++++ .../x/arch/arm64/arm64asm/decode_test.go | 78 + .../x/arch/arm64/arm64asm/ext_test.go | 601 ++ .../golang.org/x/arch/arm64/arm64asm/gnu.go | 35 + .../golang.org/x/arch/arm64/arm64asm/inst.go | 963 ++ .../x/arch/arm64/arm64asm/inst.json | 1219 +++ .../x/arch/arm64/arm64asm/objdump_test.go | 124 + .../x/arch/arm64/arm64asm/objdumpext_test.go | 299 + .../x/arch/arm64/arm64asm/plan9x.go | 611 ++ .../x/arch/arm64/arm64asm/tables.go | 3366 ++++++ .../x/arch/arm64/arm64asm/testdata/Makefile | 7 + .../x/arch/arm64/arm64asm/testdata/cases.txt | 9203 +++++++++++++++++ 19 files changed, 21603 insertions(+), 14 deletions(-) create mode 100644 src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/arg.go create mode 100755 src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/condition.go create mode 100755 src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/condition_util.go create mode 100644 src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/decode.go create mode 100644 src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/decode_test.go create mode 100644 src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/ext_test.go create mode 100644 src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/gnu.go create mode 100644 src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/inst.go create mode 100644 src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/inst.json create mode 100644 src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/objdump_test.go create mode 100644 src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/objdumpext_test.go create mode 100644 src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/plan9x.go create mode 100644 src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/tables.go create mode 100644 src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/testdata/Makefile create mode 100644 src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/testdata/cases.txt diff --git a/src/cmd/vendor/golang.org/x/arch/arm/armasm/decode.go b/src/cmd/vendor/golang.org/x/arch/arm/armasm/decode.go index cc81dc3f50..6b4d73841b 100644 --- a/src/cmd/vendor/golang.org/x/arch/arm/armasm/decode.go +++ b/src/cmd/vendor/golang.org/x/arch/arm/armasm/decode.go @@ -233,9 +233,9 @@ func decodeArg(aop instArg, x uint32) Arg { typ, count := decodeShift(x) // ROR #0 here means ROR #0, but decodeShift rewrites to RRX #1. if typ == RotateRightExt { - return Rm + return Reg(Rm) } - return RegShift{Rm, typ, count} + return RegShift{Rm, typ, uint8(count)} case arg_R_shift_R: Rm := Reg(x & (1<<4 - 1)) @@ -247,9 +247,9 @@ func decodeArg(aop instArg, x uint32) Arg { Rm := Reg(x & (1<<4 - 1)) typ, count := decodeShift(x) if typ == ShiftLeft && count == 0 { - return Rm + return Reg(Rm) } - return RegShift{Rm, typ, count} + return RegShift{Rm, typ, uint8(count)} case arg_R1_0: return Reg((x & (1<<4 - 1))) diff --git a/src/cmd/vendor/golang.org/x/arch/arm/armasm/plan9x.go b/src/cmd/vendor/golang.org/x/arch/arm/armasm/plan9x.go index fae0ca62a5..321b081505 100644 --- a/src/cmd/vendor/golang.org/x/arch/arm/armasm/plan9x.go +++ b/src/cmd/vendor/golang.org/x/arch/arm/armasm/plan9x.go @@ -9,6 +9,7 @@ import ( "encoding/binary" "fmt" "io" + "math" "strings" ) @@ -37,7 +38,7 @@ func GoSyntax(inst Inst, pc uint64, symname func(uint64) (string, uint64), text op := inst.Op.String() switch inst.Op &^ 15 { - case LDR_EQ, LDRB_EQ, LDRH_EQ: + case LDR_EQ, LDRB_EQ, LDRH_EQ, LDRSB_EQ, LDRSH_EQ, VLDR_EQ: // Check for RET reg, _ := inst.Args[0].(Reg) mem, _ := inst.Args[1].(Mem) @@ -48,22 +49,22 @@ func GoSyntax(inst Inst, pc uint64, symname func(uint64) (string, uint64), text // Check for PC-relative load. if mem.Base == PC && mem.Sign == 0 && mem.Mode == AddrOffset && text != nil { addr := uint32(pc) + 8 + uint32(mem.Offset) - buf := make([]byte, 4) + buf := make([]byte, 8) switch inst.Op &^ 15 { - case LDRB_EQ: + case LDRB_EQ, LDRSB_EQ: if _, err := text.ReadAt(buf[:1], int64(addr)); err != nil { break } args[1] = fmt.Sprintf("$%#x", buf[0]) - case LDRH_EQ: + case LDRH_EQ, LDRSH_EQ: if _, err := text.ReadAt(buf[:2], int64(addr)); err != nil { break } args[1] = fmt.Sprintf("$%#x", binary.LittleEndian.Uint16(buf)) case LDR_EQ: - if _, err := text.ReadAt(buf, int64(addr)); err != nil { + if _, err := text.ReadAt(buf[:4], int64(addr)); err != nil { break } x := binary.LittleEndian.Uint32(buf) @@ -72,6 +73,22 @@ func GoSyntax(inst Inst, pc uint64, symname func(uint64) (string, uint64), text } else { args[1] = fmt.Sprintf("$%#x", x) } + + case VLDR_EQ: + switch { + case strings.HasPrefix(args[0], "D"): // VLDR.F64 + if _, err := text.ReadAt(buf, int64(addr)); err != nil { + break + } + args[1] = fmt.Sprintf("$%f", math.Float64frombits(binary.LittleEndian.Uint64(buf))) + case strings.HasPrefix(args[0], "S"): // VLDR.F32 + if _, err := text.ReadAt(buf[:4], int64(addr)); err != nil { + break + } + args[1] = fmt.Sprintf("$%f", math.Float32frombits(binary.LittleEndian.Uint32(buf))) + default: + panic(fmt.Sprintf("wrong FP register: %v", inst)) + } } } } @@ -79,7 +96,7 @@ func GoSyntax(inst Inst, pc uint64, symname func(uint64) (string, uint64), text // Move addressing mode into opcode suffix. suffix := "" switch inst.Op &^ 15 { - case LDR_EQ, LDRB_EQ, LDRH_EQ, STR_EQ, STRB_EQ, STRH_EQ: + case LDR_EQ, LDRB_EQ, LDRSB_EQ, LDRH_EQ, LDRSH_EQ, STR_EQ, STRB_EQ, STRH_EQ, VLDR_EQ, VSTR_EQ: mem, _ := inst.Args[1].(Mem) switch mem.Mode { case AddrOffset, AddrLDM: @@ -98,7 +115,7 @@ func GoSyntax(inst Inst, pc uint64, symname func(uint64) (string, uint64), text if mem.Sign != 0 { sign := "" if mem.Sign < 0 { - sign = "" + suffix += ".U" } shift := "" if mem.Count != 0 { @@ -113,6 +130,11 @@ func GoSyntax(inst Inst, pc uint64, symname func(uint64) (string, uint64), text for i, j := 0, len(args)-1; i < j; i, j = i+1, j-1 { args[i], args[j] = args[j], args[i] } + // For MLA-like instructions, the addend is the third operand. + switch inst.Op &^ 15 { + case SMLAWT_EQ, SMLAWB_EQ, MLA_EQ, MLA_S_EQ, MLS_EQ, SMMLA_EQ, SMMLS_EQ, SMLABB_EQ, SMLATB_EQ, SMLABT_EQ, SMLATT_EQ, SMLAD_EQ, SMLAD_X_EQ, SMLSD_EQ, SMLSD_X_EQ: + args = []string{args[1], args[2], args[0], args[3]} + } switch inst.Op &^ 15 { case MOV_EQ: @@ -121,9 +143,26 @@ func GoSyntax(inst Inst, pc uint64, symname func(uint64) (string, uint64), text case LDR_EQ: op = "MOVW" + op[3:] + suffix case LDRB_EQ: - op = "MOVB" + op[4:] + suffix + op = "MOVBU" + op[4:] + suffix + case LDRSB_EQ: + op = "MOVBS" + op[5:] + suffix case LDRH_EQ: - op = "MOVH" + op[4:] + suffix + op = "MOVHU" + op[4:] + suffix + case LDRSH_EQ: + op = "MOVHS" + op[5:] + suffix + case VLDR_EQ: + switch { + case strings.HasPrefix(args[1], "D"): // VLDR.F64 + op = "MOVD" + op[4:] + suffix + args[1] = "F" + args[1][1:] // Dx -> Fx + case strings.HasPrefix(args[1], "S"): // VLDR.F32 + op = "MOVF" + op[4:] + suffix + if inst.Args[0].(Reg)&1 == 0 { // Sx -> Fy, y = x/2, if x is even + args[1] = fmt.Sprintf("F%d", (inst.Args[0].(Reg)-S0)/2) + } + default: + panic(fmt.Sprintf("wrong FP register: %v", inst)) + } case STR_EQ: op = "MOVW" + op[3:] + suffix @@ -134,6 +173,20 @@ func GoSyntax(inst Inst, pc uint64, symname func(uint64) (string, uint64), text case STRH_EQ: op = "MOVH" + op[4:] + suffix args[0], args[1] = args[1], args[0] + case VSTR_EQ: + switch { + case strings.HasPrefix(args[1], "D"): // VSTR.F64 + op = "MOVD" + op[4:] + suffix + args[1] = "F" + args[1][1:] // Dx -> Fx + case strings.HasPrefix(args[1], "S"): // VSTR.F32 + op = "MOVF" + op[4:] + suffix + if inst.Args[0].(Reg)&1 == 0 { // Sx -> Fy, y = x/2, if x is even + args[1] = fmt.Sprintf("F%d", (inst.Args[0].(Reg)-S0)/2) + } + default: + panic(fmt.Sprintf("wrong FP register: %v", inst)) + } + args[0], args[1] = args[1], args[0] } if args != nil { @@ -154,7 +207,7 @@ func plan9Arg(inst *Inst, pc uint64, symname func(uint64) (string, uint64), arg case Endian: case Imm: - return fmt.Sprintf("$%d", int(a)) + return fmt.Sprintf("$%d", uint32(a)) case Mem: @@ -185,6 +238,8 @@ func plan9Arg(inst *Inst, pc uint64, symname func(uint64) (string, uint64), arg } else { fmt.Fprintf(&buf, "R%d-R%d", start, end) } + start = -2 + end = -2 } } for i := 0; i < 16; i++ { @@ -195,6 +250,8 @@ func plan9Arg(inst *Inst, pc uint64, symname func(uint64) (string, uint64), arg } start = i end = i + } else { + flush() } } flush() diff --git a/src/cmd/vendor/golang.org/x/arch/arm/armasm/tables.go b/src/cmd/vendor/golang.org/x/arch/arm/armasm/tables.go index 58f51fe1f5..3ad489e019 100644 --- a/src/cmd/vendor/golang.org/x/arch/arm/armasm/tables.go +++ b/src/cmd/vendor/golang.org/x/arch/arm/armasm/tables.go @@ -945,6 +945,22 @@ const ( MRS_LE MRS MRS_ZZ + MSR_EQ + MSR_NE + MSR_CS + MSR_CC + MSR_MI + MSR_PL + MSR_VS + MSR_VC + MSR_HI + MSR_LS + MSR_GE + MSR_LT + MSR_GT + MSR_LE + MSR + MSR_ZZ MUL_EQ MUL_NE MUL_CS @@ -1585,6 +1601,22 @@ const ( SBFX_LE SBFX SBFX_ZZ + SDIV_EQ + SDIV_NE + SDIV_CS + SDIV_CC + SDIV_MI + SDIV_PL + SDIV_VS + SDIV_VC + SDIV_HI + SDIV_LS + SDIV_GE + SDIV_LT + SDIV_GT + SDIV_LE + SDIV + SDIV_ZZ SEL_EQ SEL_NE SEL_CS @@ -2929,6 +2961,22 @@ const ( UBFX_LE UBFX UBFX_ZZ + UDIV_EQ + UDIV_NE + UDIV_CS + UDIV_CC + UDIV_MI + UDIV_PL + UDIV_VS + UDIV_VC + UDIV_HI + UDIV_LS + UDIV_GE + UDIV_LT + UDIV_GT + UDIV_LE + UDIV + UDIV_ZZ UHADD16_EQ UHADD16_NE UHADD16_CS @@ -5480,6 +5528,22 @@ var opstr = [...]string{ MRS_LE: "MRS.LE", MRS: "MRS", MRS_ZZ: "MRS.ZZ", + MSR_EQ: "MSR.EQ", + MSR_NE: "MSR.NE", + MSR_CS: "MSR.CS", + MSR_CC: "MSR.CC", + MSR_MI: "MSR.MI", + MSR_PL: "MSR.PL", + MSR_VS: "MSR.VS", + MSR_VC: "MSR.VC", + MSR_HI: "MSR.HI", + MSR_LS: "MSR.LS", + MSR_GE: "MSR.GE", + MSR_LT: "MSR.LT", + MSR_GT: "MSR.GT", + MSR_LE: "MSR.LE", + MSR: "MSR", + MSR_ZZ: "MSR.ZZ", MUL_EQ: "MUL.EQ", MUL_NE: "MUL.NE", MUL_CS: "MUL.CS", @@ -6107,6 +6171,22 @@ var opstr = [...]string{ SBFX_LE: "SBFX.LE", SBFX: "SBFX", SBFX_ZZ: "SBFX.ZZ", + SDIV_EQ: "SDIV.EQ", + SDIV_NE: "SDIV.NE", + SDIV_CS: "SDIV.CS", + SDIV_CC: "SDIV.CC", + SDIV_MI: "SDIV.MI", + SDIV_PL: "SDIV.PL", + SDIV_VS: "SDIV.VS", + SDIV_VC: "SDIV.VC", + SDIV_HI: "SDIV.HI", + SDIV_LS: "SDIV.LS", + SDIV_GE: "SDIV.GE", + SDIV_LT: "SDIV.LT", + SDIV_GT: "SDIV.GT", + SDIV_LE: "SDIV.LE", + SDIV: "SDIV", + SDIV_ZZ: "SDIV.ZZ", SEL_EQ: "SEL.EQ", SEL_NE: "SEL.NE", SEL_CS: "SEL.CS", @@ -7436,6 +7516,22 @@ var opstr = [...]string{ UBFX_LE: "UBFX.LE", UBFX: "UBFX", UBFX_ZZ: "UBFX.ZZ", + UDIV_EQ: "UDIV.EQ", + UDIV_NE: "UDIV.NE", + UDIV_CS: "UDIV.CS", + UDIV_CC: "UDIV.CC", + UDIV_MI: "UDIV.MI", + UDIV_PL: "UDIV.PL", + UDIV_VS: "UDIV.VS", + UDIV_VC: "UDIV.VC", + UDIV_HI: "UDIV.HI", + UDIV_LS: "UDIV.LS", + UDIV_GE: "UDIV.GE", + UDIV_LT: "UDIV.LT", + UDIV_GT: "UDIV.GT", + UDIV_LE: "UDIV.LE", + UDIV: "UDIV", + UDIV_ZZ: "UDIV.ZZ", UHADD16_EQ: "UHADD16.EQ", UHADD16_NE: "UHADD16.NE", UHADD16_CS: "UHADD16.CS", @@ -9194,6 +9290,10 @@ var instFormats = [...]instFormat{ {0x0fef0ff0, 0x01a00000, 2, MOV_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_0}}, // MOV{S} , cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|0|0|0|0|0|0|0|0|Rm:4 {0x0fff0fff, 0x010f0000, 4, MRS_EQ, 0x1c04, instArgs{arg_R_12, arg_APSR}}, // MRS ,APSR cond:4|0|0|0|1|0|0|0|0|(1)|(1)|(1)|(1)|Rd:4|(0)|(0)|(0)|(0)|0|0|0|0|(0)|(0)|(0)|(0) {0x0ff000f0, 0x010f0000, 3, MRS_EQ, 0x1c04, instArgs{arg_R_12, arg_APSR}}, // MRS ,APSR cond:4|0|0|0|1|0|0|0|0|(1)|(1)|(1)|(1)|Rd:4|(0)|(0)|(0)|(0)|0|0|0|0|(0)|(0)|(0)|(0) + {0x0ffffff0, 0x012cf000, 4, MSR_EQ, 0x1c04, instArgs{arg_APSR, arg_R_0}}, // MSR APSR, cond:4|0|0|0|1|0|0|1|0|1|1|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|Rn:4 + {0x0fff00f0, 0x012cf000, 3, MSR_EQ, 0x1c04, instArgs{arg_APSR, arg_R_0}}, // MSR APSR, cond:4|0|0|0|1|0|0|1|0|1|1|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|Rn:4 + {0x0ffff000, 0x032cf000, 4, MSR_EQ, 0x1c04, instArgs{arg_APSR, arg_const}}, // MSR APSR,# cond:4|0|0|1|1|0|0|1|0|1|1|0|0|(1)|(1)|(1)|(1)|imm12:12 + {0x0fff0000, 0x032cf000, 3, MSR_EQ, 0x1c04, instArgs{arg_APSR, arg_const}}, // MSR APSR,# cond:4|0|0|1|1|0|0|1|0|1|1|0|0|(1)|(1)|(1)|(1)|imm12:12 {0x0fe0f0f0, 0x00000090, 4, MUL_EQ, 0x14011c04, instArgs{arg_R_16, arg_R_0, arg_R_8}}, // MUL{S} ,, cond:4|0|0|0|0|0|0|0|S|Rd:4|(0)|(0)|(0)|(0)|Rm:4|1|0|0|1|Rn:4 {0x0fe000f0, 0x00000090, 3, MUL_EQ, 0x14011c04, instArgs{arg_R_16, arg_R_0, arg_R_8}}, // MUL{S} ,, cond:4|0|0|0|0|0|0|0|S|Rd:4|(0)|(0)|(0)|(0)|Rm:4|1|0|0|1|Rn:4 {0x0fef0000, 0x03e00000, 2, MVN_EQ, 0x14011c04, instArgs{arg_R_12, arg_const}}, // MVN{S} ,# cond:4|0|0|1|1|1|1|1|S|(0)|(0)|(0)|(0)|Rd:4|imm12:12 @@ -9267,6 +9367,8 @@ var instFormats = [...]instFormat{ {0x0fe00090, 0x00c00010, 4, SBC_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_R}}, // SBC{S} ,,, cond:4|0|0|0|0|1|1|0|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4 {0x0fe00010, 0x00c00000, 2, SBC_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_imm}}, // SBC{S} ,,{,} cond:4|0|0|0|0|1|1|0|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4 {0x0fe00070, 0x07a00050, 4, SBFX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0, arg_imm5, arg_widthm1}}, // SBFX ,,#,# cond:4|0|1|1|1|1|0|1|widthm1:5|Rd:4|lsb:5|1|0|1|Rn:4 + {0x0ff0f0f0, 0x0710f010, 4, SDIV_EQ, 0x1c04, instArgs{arg_R_16, arg_R_0, arg_R_8}}, // SDIV ,, cond:4|0|1|1|1|0|0|0|1|Rd:4|(1)|(1)|(1)|(1)|Rm:4|0|0|0|1|Rn:4 + {0x0ff000f0, 0x0710f010, 3, SDIV_EQ, 0x1c04, instArgs{arg_R_16, arg_R_0, arg_R_8}}, // SDIV ,, cond:4|0|1|1|1|0|0|0|1|Rd:4|(1)|(1)|(1)|(1)|Rm:4|0|0|0|1|Rn:4 {0x0ff00ff0, 0x06800fb0, 4, SEL_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SEL ,, cond:4|0|1|1|0|1|0|0|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|1|1|Rm:4 {0x0ff000f0, 0x06800fb0, 3, SEL_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SEL ,, cond:4|0|1|1|0|1|0|0|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|1|1|Rm:4 {0xfffffdff, 0xf1010000, 4, SETEND, 0x0, instArgs{arg_endian}}, // SETEND 1|1|1|1|0|0|0|1|0|0|0|0|0|0|0|1|0|0|0|0|0|0|E|(0)|(0)|(0)|(0)|(0)|(0)|(0)|(0)|(0) @@ -9365,6 +9467,8 @@ var instFormats = [...]instFormat{ {0x0ff00ff0, 0x06500f30, 4, UASX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UASX ,, cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 {0x0ff000f0, 0x06500f30, 3, UASX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UASX ,, cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 {0x0fe00070, 0x07e00050, 4, UBFX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0, arg_imm5, arg_widthm1}}, // UBFX ,,#,# cond:4|0|1|1|1|1|1|1|widthm1:5|Rd:4|lsb:5|1|0|1|Rn:4 + {0x0ff0f0f0, 0x0730f010, 4, UDIV_EQ, 0x1c04, instArgs{arg_R_16, arg_R_0, arg_R_8}}, // UDIV ,, cond:4|0|1|1|1|0|0|1|1|Rd:4|(1)|(1)|(1)|(1)|Rm:4|0|0|0|1|Rn:4 + {0x0ff000f0, 0x0730f010, 3, UDIV_EQ, 0x1c04, instArgs{arg_R_16, arg_R_0, arg_R_8}}, // UDIV ,, cond:4|0|1|1|1|0|0|1|1|Rd:4|(1)|(1)|(1)|(1)|Rm:4|0|0|0|1|Rn:4 {0x0ff00ff0, 0x06700f10, 4, UHADD16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UHADD16 ,, cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 {0x0ff000f0, 0x06700f10, 3, UHADD16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UHADD16 ,, cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 {0x0ff00ff0, 0x06700f90, 4, UHADD8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UHADD8 ,, cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4 diff --git a/src/cmd/vendor/golang.org/x/arch/arm/armasm/testdata/decode.txt b/src/cmd/vendor/golang.org/x/arch/arm/armasm/testdata/decode.txt index cc1ea0abe5..f38c61f7be 100644 --- a/src/cmd/vendor/golang.org/x/arch/arm/armasm/testdata/decode.txt +++ b/src/cmd/vendor/golang.org/x/arch/arm/armasm/testdata/decode.txt @@ -304,3 +304,1253 @@ ff818c71| 1 gnu strdvc r8, [ip, pc] |6b5721d3 1 gnu error: unknown instruction |76452001 1 gnu error: unknown instruction |97acd647 1 gnu error: unknown instruction +11f71507| 1 plan9 SDIV.EQ R7, R1, R5 +15f715e7| 1 plan9 SDIV R7, R5, R5 +11f93517| 1 plan9 UDIV.NE R9, R1, R5 +12fb33e7| 1 plan9 UDIV R11, R2, R3 +ed003be9| 1 plan9 LDMDB [R0,R2-R3,R5-R7], R11! +923124e0| 1 plan9 MLA R1, R2, R3, R4 +923134e0| 1 plan9 MLA.S R1, R2, R3, R4 +923164e0| 1 plan9 MLS R1, R2, R3, R4 +ff1000e2| 1 plan9 AND $255, R0, R1 +ff1400e2| 1 plan9 AND $4278190080, R0, R1 +ff1010e2| 1 plan9 AND.S $255, R0, R1 +ff1410e2| 1 plan9 AND.S $4278190080, R0, R1 +ff0000e2| 1 plan9 AND $255, R0, R0 +ff0400e2| 1 plan9 AND $4278190080, R0, R0 +ff0010e2| 1 plan9 AND.S $255, R0, R0 +ff0410e2| 1 plan9 AND.S $4278190080, R0, R0 +002001e0| 1 plan9 AND R0, R1, R2 +002011e0| 1 plan9 AND.S R0, R1, R2 +001001e0| 1 plan9 AND R0, R1, R1 +001011e0| 1 plan9 AND.S R0, R1, R1 +202e01e0| 1 plan9 AND R0>>$28, R1, R2 +002e01e0| 1 plan9 AND R0<<$28, R1, R2 +402e01e0| 1 plan9 AND R0->$28, R1, R2 +602e01e0| 1 plan9 AND R0@>$28, R1, R2 +202e11e0| 1 plan9 AND.S R0>>$28, R1, R2 +002e11e0| 1 plan9 AND.S R0<<$28, R1, R2 +402e11e0| 1 plan9 AND.S R0->$28, R1, R2 +602e11e0| 1 plan9 AND.S R0@>$28, R1, R2 +001e01e0| 1 plan9 AND R0<<$28, R1, R1 +201e01e0| 1 plan9 AND R0>>$28, R1, R1 +401e01e0| 1 plan9 AND R0->$28, R1, R1 +601e01e0| 1 plan9 AND R0@>$28, R1, R1 +001e11e0| 1 plan9 AND.S R0<<$28, R1, R1 +201e11e0| 1 plan9 AND.S R0>>$28, R1, R1 +401e11e0| 1 plan9 AND.S R0->$28, R1, R1 +601e11e0| 1 plan9 AND.S R0@>$28, R1, R1 +103102e0| 1 plan9 AND R0<>R1, R2, R3 +503102e0| 1 plan9 AND R0->R1, R2, R3 +703102e0| 1 plan9 AND R0@>R1, R2, R3 +103112e0| 1 plan9 AND.S R0<>R1, R2, R3 +503112e0| 1 plan9 AND.S R0->R1, R2, R3 +703112e0| 1 plan9 AND.S R0@>R1, R2, R3 +102102e0| 1 plan9 AND R0<>R1, R2, R2 +502102e0| 1 plan9 AND R0->R1, R2, R2 +702102e0| 1 plan9 AND R0@>R1, R2, R2 +102112e0| 1 plan9 AND.S R0<>R1, R2, R2 +502112e0| 1 plan9 AND.S R0->R1, R2, R2 +702112e0| 1 plan9 AND.S R0@>R1, R2, R2 +ff1020e2| 1 plan9 EOR $255, R0, R1 +ff1420e2| 1 plan9 EOR $4278190080, R0, R1 +ff1030e2| 1 plan9 EOR.S $255, R0, R1 +ff1430e2| 1 plan9 EOR.S $4278190080, R0, R1 +ff0020e2| 1 plan9 EOR $255, R0, R0 +ff0420e2| 1 plan9 EOR $4278190080, R0, R0 +ff0030e2| 1 plan9 EOR.S $255, R0, R0 +ff0430e2| 1 plan9 EOR.S $4278190080, R0, R0 +002021e0| 1 plan9 EOR R0, R1, R2 +002031e0| 1 plan9 EOR.S R0, R1, R2 +001021e0| 1 plan9 EOR R0, R1, R1 +001031e0| 1 plan9 EOR.S R0, R1, R1 +202e21e0| 1 plan9 EOR R0>>$28, R1, R2 +002e21e0| 1 plan9 EOR R0<<$28, R1, R2 +402e21e0| 1 plan9 EOR R0->$28, R1, R2 +602e21e0| 1 plan9 EOR R0@>$28, R1, R2 +202e31e0| 1 plan9 EOR.S R0>>$28, R1, R2 +002e31e0| 1 plan9 EOR.S R0<<$28, R1, R2 +402e31e0| 1 plan9 EOR.S R0->$28, R1, R2 +602e31e0| 1 plan9 EOR.S R0@>$28, R1, R2 +001e21e0| 1 plan9 EOR R0<<$28, R1, R1 +201e21e0| 1 plan9 EOR R0>>$28, R1, R1 +401e21e0| 1 plan9 EOR R0->$28, R1, R1 +601e21e0| 1 plan9 EOR R0@>$28, R1, R1 +001e31e0| 1 plan9 EOR.S R0<<$28, R1, R1 +201e31e0| 1 plan9 EOR.S R0>>$28, R1, R1 +401e31e0| 1 plan9 EOR.S R0->$28, R1, R1 +601e31e0| 1 plan9 EOR.S R0@>$28, R1, R1 +103122e0| 1 plan9 EOR R0<>R1, R2, R3 +503122e0| 1 plan9 EOR R0->R1, R2, R3 +703122e0| 1 plan9 EOR R0@>R1, R2, R3 +103132e0| 1 plan9 EOR.S R0<>R1, R2, R3 +503132e0| 1 plan9 EOR.S R0->R1, R2, R3 +703132e0| 1 plan9 EOR.S R0@>R1, R2, R3 +102122e0| 1 plan9 EOR R0<>R1, R2, R2 +502122e0| 1 plan9 EOR R0->R1, R2, R2 +702122e0| 1 plan9 EOR R0@>R1, R2, R2 +102132e0| 1 plan9 EOR.S R0<>R1, R2, R2 +502132e0| 1 plan9 EOR.S R0->R1, R2, R2 +702132e0| 1 plan9 EOR.S R0@>R1, R2, R2 +ff1080e3| 1 plan9 ORR $255, R0, R1 +ff1480e3| 1 plan9 ORR $4278190080, R0, R1 +ff1090e3| 1 plan9 ORR.S $255, R0, R1 +ff1490e3| 1 plan9 ORR.S $4278190080, R0, R1 +ff0080e3| 1 plan9 ORR $255, R0, R0 +ff0480e3| 1 plan9 ORR $4278190080, R0, R0 +ff0090e3| 1 plan9 ORR.S $255, R0, R0 +ff0490e3| 1 plan9 ORR.S $4278190080, R0, R0 +002081e1| 1 plan9 ORR R0, R1, R2 +002091e1| 1 plan9 ORR.S R0, R1, R2 +001081e1| 1 plan9 ORR R0, R1, R1 +001091e1| 1 plan9 ORR.S R0, R1, R1 +202e81e1| 1 plan9 ORR R0>>$28, R1, R2 +002e81e1| 1 plan9 ORR R0<<$28, R1, R2 +402e81e1| 1 plan9 ORR R0->$28, R1, R2 +602e81e1| 1 plan9 ORR R0@>$28, R1, R2 +202e91e1| 1 plan9 ORR.S R0>>$28, R1, R2 +002e91e1| 1 plan9 ORR.S R0<<$28, R1, R2 +402e91e1| 1 plan9 ORR.S R0->$28, R1, R2 +602e91e1| 1 plan9 ORR.S R0@>$28, R1, R2 +001e81e1| 1 plan9 ORR R0<<$28, R1, R1 +201e81e1| 1 plan9 ORR R0>>$28, R1, R1 +401e81e1| 1 plan9 ORR R0->$28, R1, R1 +601e81e1| 1 plan9 ORR R0@>$28, R1, R1 +001e91e1| 1 plan9 ORR.S R0<<$28, R1, R1 +201e91e1| 1 plan9 ORR.S R0>>$28, R1, R1 +401e91e1| 1 plan9 ORR.S R0->$28, R1, R1 +601e91e1| 1 plan9 ORR.S R0@>$28, R1, R1 +103182e1| 1 plan9 ORR R0<>R1, R2, R3 +503182e1| 1 plan9 ORR R0->R1, R2, R3 +703182e1| 1 plan9 ORR R0@>R1, R2, R3 +103192e1| 1 plan9 ORR.S R0<>R1, R2, R3 +503192e1| 1 plan9 ORR.S R0->R1, R2, R3 +703192e1| 1 plan9 ORR.S R0@>R1, R2, R3 +102182e1| 1 plan9 ORR R0<>R1, R2, R2 +502182e1| 1 plan9 ORR R0->R1, R2, R2 +702182e1| 1 plan9 ORR R0@>R1, R2, R2 +102192e1| 1 plan9 ORR.S R0<>R1, R2, R2 +502192e1| 1 plan9 ORR.S R0->R1, R2, R2 +702192e1| 1 plan9 ORR.S R0@>R1, R2, R2 +ff1040e2| 1 plan9 SUB $255, R0, R1 +ff1440e2| 1 plan9 SUB $4278190080, R0, R1 +ff1050e2| 1 plan9 SUB.S $255, R0, R1 +ff1450e2| 1 plan9 SUB.S $4278190080, R0, R1 +ff0040e2| 1 plan9 SUB $255, R0, R0 +ff0440e2| 1 plan9 SUB $4278190080, R0, R0 +ff0050e2| 1 plan9 SUB.S $255, R0, R0 +ff0450e2| 1 plan9 SUB.S $4278190080, R0, R0 +002041e0| 1 plan9 SUB R0, R1, R2 +002051e0| 1 plan9 SUB.S R0, R1, R2 +001041e0| 1 plan9 SUB R0, R1, R1 +001051e0| 1 plan9 SUB.S R0, R1, R1 +202e41e0| 1 plan9 SUB R0>>$28, R1, R2 +002e41e0| 1 plan9 SUB R0<<$28, R1, R2 +402e41e0| 1 plan9 SUB R0->$28, R1, R2 +602e41e0| 1 plan9 SUB R0@>$28, R1, R2 +202e51e0| 1 plan9 SUB.S R0>>$28, R1, R2 +002e51e0| 1 plan9 SUB.S R0<<$28, R1, R2 +402e51e0| 1 plan9 SUB.S R0->$28, R1, R2 +602e51e0| 1 plan9 SUB.S R0@>$28, R1, R2 +001e41e0| 1 plan9 SUB R0<<$28, R1, R1 +201e41e0| 1 plan9 SUB R0>>$28, R1, R1 +401e41e0| 1 plan9 SUB R0->$28, R1, R1 +601e41e0| 1 plan9 SUB R0@>$28, R1, R1 +001e51e0| 1 plan9 SUB.S R0<<$28, R1, R1 +201e51e0| 1 plan9 SUB.S R0>>$28, R1, R1 +401e51e0| 1 plan9 SUB.S R0->$28, R1, R1 +601e51e0| 1 plan9 SUB.S R0@>$28, R1, R1 +103142e0| 1 plan9 SUB R0<>R1, R2, R3 +503142e0| 1 plan9 SUB R0->R1, R2, R3 +703142e0| 1 plan9 SUB R0@>R1, R2, R3 +103152e0| 1 plan9 SUB.S R0<>R1, R2, R3 +503152e0| 1 plan9 SUB.S R0->R1, R2, R3 +703152e0| 1 plan9 SUB.S R0@>R1, R2, R3 +102142e0| 1 plan9 SUB R0<>R1, R2, R2 +502142e0| 1 plan9 SUB R0->R1, R2, R2 +702142e0| 1 plan9 SUB R0@>R1, R2, R2 +102152e0| 1 plan9 SUB.S R0<>R1, R2, R2 +502152e0| 1 plan9 SUB.S R0->R1, R2, R2 +702152e0| 1 plan9 SUB.S R0@>R1, R2, R2 +ff10c0e2| 1 plan9 SBC $255, R0, R1 +ff14c0e2| 1 plan9 SBC $4278190080, R0, R1 +ff10d0e2| 1 plan9 SBC.S $255, R0, R1 +ff14d0e2| 1 plan9 SBC.S $4278190080, R0, R1 +ff00c0e2| 1 plan9 SBC $255, R0, R0 +ff04c0e2| 1 plan9 SBC $4278190080, R0, R0 +ff00d0e2| 1 plan9 SBC.S $255, R0, R0 +ff04d0e2| 1 plan9 SBC.S $4278190080, R0, R0 +0020c1e0| 1 plan9 SBC R0, R1, R2 +0020d1e0| 1 plan9 SBC.S R0, R1, R2 +0010c1e0| 1 plan9 SBC R0, R1, R1 +0010d1e0| 1 plan9 SBC.S R0, R1, R1 +202ec1e0| 1 plan9 SBC R0>>$28, R1, R2 +002ec1e0| 1 plan9 SBC R0<<$28, R1, R2 +402ec1e0| 1 plan9 SBC R0->$28, R1, R2 +602ec1e0| 1 plan9 SBC R0@>$28, R1, R2 +202ed1e0| 1 plan9 SBC.S R0>>$28, R1, R2 +002ed1e0| 1 plan9 SBC.S R0<<$28, R1, R2 +402ed1e0| 1 plan9 SBC.S R0->$28, R1, R2 +602ed1e0| 1 plan9 SBC.S R0@>$28, R1, R2 +001ec1e0| 1 plan9 SBC R0<<$28, R1, R1 +201ec1e0| 1 plan9 SBC R0>>$28, R1, R1 +401ec1e0| 1 plan9 SBC R0->$28, R1, R1 +601ec1e0| 1 plan9 SBC R0@>$28, R1, R1 +001ed1e0| 1 plan9 SBC.S R0<<$28, R1, R1 +201ed1e0| 1 plan9 SBC.S R0>>$28, R1, R1 +401ed1e0| 1 plan9 SBC.S R0->$28, R1, R1 +601ed1e0| 1 plan9 SBC.S R0@>$28, R1, R1 +1031c2e0| 1 plan9 SBC R0<>R1, R2, R3 +5031c2e0| 1 plan9 SBC R0->R1, R2, R3 +7031c2e0| 1 plan9 SBC R0@>R1, R2, R3 +1031d2e0| 1 plan9 SBC.S R0<>R1, R2, R3 +5031d2e0| 1 plan9 SBC.S R0->R1, R2, R3 +7031d2e0| 1 plan9 SBC.S R0@>R1, R2, R3 +1021c2e0| 1 plan9 SBC R0<>R1, R2, R2 +5021c2e0| 1 plan9 SBC R0->R1, R2, R2 +7021c2e0| 1 plan9 SBC R0@>R1, R2, R2 +1021d2e0| 1 plan9 SBC.S R0<>R1, R2, R2 +5021d2e0| 1 plan9 SBC.S R0->R1, R2, R2 +7021d2e0| 1 plan9 SBC.S R0@>R1, R2, R2 +ff1060e2| 1 plan9 RSB $255, R0, R1 +ff1460e2| 1 plan9 RSB $4278190080, R0, R1 +ff1070e2| 1 plan9 RSB.S $255, R0, R1 +ff1470e2| 1 plan9 RSB.S $4278190080, R0, R1 +ff0060e2| 1 plan9 RSB $255, R0, R0 +ff0460e2| 1 plan9 RSB $4278190080, R0, R0 +ff0070e2| 1 plan9 RSB.S $255, R0, R0 +ff0470e2| 1 plan9 RSB.S $4278190080, R0, R0 +002061e0| 1 plan9 RSB R0, R1, R2 +002071e0| 1 plan9 RSB.S R0, R1, R2 +001061e0| 1 plan9 RSB R0, R1, R1 +001071e0| 1 plan9 RSB.S R0, R1, R1 +202e61e0| 1 plan9 RSB R0>>$28, R1, R2 +002e61e0| 1 plan9 RSB R0<<$28, R1, R2 +402e61e0| 1 plan9 RSB R0->$28, R1, R2 +602e61e0| 1 plan9 RSB R0@>$28, R1, R2 +202e71e0| 1 plan9 RSB.S R0>>$28, R1, R2 +002e71e0| 1 plan9 RSB.S R0<<$28, R1, R2 +402e71e0| 1 plan9 RSB.S R0->$28, R1, R2 +602e71e0| 1 plan9 RSB.S R0@>$28, R1, R2 +001e61e0| 1 plan9 RSB R0<<$28, R1, R1 +201e61e0| 1 plan9 RSB R0>>$28, R1, R1 +401e61e0| 1 plan9 RSB R0->$28, R1, R1 +601e61e0| 1 plan9 RSB R0@>$28, R1, R1 +001e71e0| 1 plan9 RSB.S R0<<$28, R1, R1 +201e71e0| 1 plan9 RSB.S R0>>$28, R1, R1 +401e71e0| 1 plan9 RSB.S R0->$28, R1, R1 +601e71e0| 1 plan9 RSB.S R0@>$28, R1, R1 +103162e0| 1 plan9 RSB R0<>R1, R2, R3 +503162e0| 1 plan9 RSB R0->R1, R2, R3 +703162e0| 1 plan9 RSB R0@>R1, R2, R3 +103172e0| 1 plan9 RSB.S R0<>R1, R2, R3 +503172e0| 1 plan9 RSB.S R0->R1, R2, R3 +703172e0| 1 plan9 RSB.S R0@>R1, R2, R3 +102162e0| 1 plan9 RSB R0<>R1, R2, R2 +502162e0| 1 plan9 RSB R0->R1, R2, R2 +702162e0| 1 plan9 RSB R0@>R1, R2, R2 +102172e0| 1 plan9 RSB.S R0<>R1, R2, R2 +502172e0| 1 plan9 RSB.S R0->R1, R2, R2 +702172e0| 1 plan9 RSB.S R0@>R1, R2, R2 +ff10e0e2| 1 plan9 RSC $255, R0, R1 +ff14e0e2| 1 plan9 RSC $4278190080, R0, R1 +ff10f0e2| 1 plan9 RSC.S $255, R0, R1 +ff14f0e2| 1 plan9 RSC.S $4278190080, R0, R1 +ff00e0e2| 1 plan9 RSC $255, R0, R0 +ff04e0e2| 1 plan9 RSC $4278190080, R0, R0 +ff00f0e2| 1 plan9 RSC.S $255, R0, R0 +ff04f0e2| 1 plan9 RSC.S $4278190080, R0, R0 +0020e1e0| 1 plan9 RSC R0, R1, R2 +0020f1e0| 1 plan9 RSC.S R0, R1, R2 +0010e1e0| 1 plan9 RSC R0, R1, R1 +0010f1e0| 1 plan9 RSC.S R0, R1, R1 +202ee1e0| 1 plan9 RSC R0>>$28, R1, R2 +002ee1e0| 1 plan9 RSC R0<<$28, R1, R2 +402ee1e0| 1 plan9 RSC R0->$28, R1, R2 +602ee1e0| 1 plan9 RSC R0@>$28, R1, R2 +202ef1e0| 1 plan9 RSC.S R0>>$28, R1, R2 +002ef1e0| 1 plan9 RSC.S R0<<$28, R1, R2 +402ef1e0| 1 plan9 RSC.S R0->$28, R1, R2 +602ef1e0| 1 plan9 RSC.S R0@>$28, R1, R2 +001ee1e0| 1 plan9 RSC R0<<$28, R1, R1 +201ee1e0| 1 plan9 RSC R0>>$28, R1, R1 +401ee1e0| 1 plan9 RSC R0->$28, R1, R1 +601ee1e0| 1 plan9 RSC R0@>$28, R1, R1 +001ef1e0| 1 plan9 RSC.S R0<<$28, R1, R1 +201ef1e0| 1 plan9 RSC.S R0>>$28, R1, R1 +401ef1e0| 1 plan9 RSC.S R0->$28, R1, R1 +601ef1e0| 1 plan9 RSC.S R0@>$28, R1, R1 +1031e2e0| 1 plan9 RSC R0<>R1, R2, R3 +5031e2e0| 1 plan9 RSC R0->R1, R2, R3 +7031e2e0| 1 plan9 RSC R0@>R1, R2, R3 +1031f2e0| 1 plan9 RSC.S R0<>R1, R2, R3 +5031f2e0| 1 plan9 RSC.S R0->R1, R2, R3 +7031f2e0| 1 plan9 RSC.S R0@>R1, R2, R3 +1021e2e0| 1 plan9 RSC R0<>R1, R2, R2 +5021e2e0| 1 plan9 RSC R0->R1, R2, R2 +7021e2e0| 1 plan9 RSC R0@>R1, R2, R2 +1021f2e0| 1 plan9 RSC.S R0<>R1, R2, R2 +5021f2e0| 1 plan9 RSC.S R0->R1, R2, R2 +7021f2e0| 1 plan9 RSC.S R0@>R1, R2, R2 +ff1080e2| 1 plan9 ADD $255, R0, R1 +ff1480e2| 1 plan9 ADD $4278190080, R0, R1 +ff1090e2| 1 plan9 ADD.S $255, R0, R1 +ff1490e2| 1 plan9 ADD.S $4278190080, R0, R1 +ff0080e2| 1 plan9 ADD $255, R0, R0 +ff0480e2| 1 plan9 ADD $4278190080, R0, R0 +ff0090e2| 1 plan9 ADD.S $255, R0, R0 +ff0490e2| 1 plan9 ADD.S $4278190080, R0, R0 +002081e0| 1 plan9 ADD R0, R1, R2 +002091e0| 1 plan9 ADD.S R0, R1, R2 +001081e0| 1 plan9 ADD R0, R1, R1 +001091e0| 1 plan9 ADD.S R0, R1, R1 +202e81e0| 1 plan9 ADD R0>>$28, R1, R2 +002e81e0| 1 plan9 ADD R0<<$28, R1, R2 +402e81e0| 1 plan9 ADD R0->$28, R1, R2 +602e81e0| 1 plan9 ADD R0@>$28, R1, R2 +202e91e0| 1 plan9 ADD.S R0>>$28, R1, R2 +002e91e0| 1 plan9 ADD.S R0<<$28, R1, R2 +402e91e0| 1 plan9 ADD.S R0->$28, R1, R2 +602e91e0| 1 plan9 ADD.S R0@>$28, R1, R2 +001e81e0| 1 plan9 ADD R0<<$28, R1, R1 +201e81e0| 1 plan9 ADD R0>>$28, R1, R1 +401e81e0| 1 plan9 ADD R0->$28, R1, R1 +601e81e0| 1 plan9 ADD R0@>$28, R1, R1 +001e91e0| 1 plan9 ADD.S R0<<$28, R1, R1 +201e91e0| 1 plan9 ADD.S R0>>$28, R1, R1 +401e91e0| 1 plan9 ADD.S R0->$28, R1, R1 +601e91e0| 1 plan9 ADD.S R0@>$28, R1, R1 +103182e0| 1 plan9 ADD R0<>R1, R2, R3 +503182e0| 1 plan9 ADD R0->R1, R2, R3 +703182e0| 1 plan9 ADD R0@>R1, R2, R3 +103192e0| 1 plan9 ADD.S R0<>R1, R2, R3 +503192e0| 1 plan9 ADD.S R0->R1, R2, R3 +703192e0| 1 plan9 ADD.S R0@>R1, R2, R3 +102182e0| 1 plan9 ADD R0<>R1, R2, R2 +502182e0| 1 plan9 ADD R0->R1, R2, R2 +702182e0| 1 plan9 ADD R0@>R1, R2, R2 +102192e0| 1 plan9 ADD.S R0<>R1, R2, R2 +502192e0| 1 plan9 ADD.S R0->R1, R2, R2 +702192e0| 1 plan9 ADD.S R0@>R1, R2, R2 +ff10a0e2| 1 plan9 ADC $255, R0, R1 +ff14a0e2| 1 plan9 ADC $4278190080, R0, R1 +ff10b0e2| 1 plan9 ADC.S $255, R0, R1 +ff14b0e2| 1 plan9 ADC.S $4278190080, R0, R1 +ff00a0e2| 1 plan9 ADC $255, R0, R0 +ff04a0e2| 1 plan9 ADC $4278190080, R0, R0 +ff00b0e2| 1 plan9 ADC.S $255, R0, R0 +ff04b0e2| 1 plan9 ADC.S $4278190080, R0, R0 +0020a1e0| 1 plan9 ADC R0, R1, R2 +0020b1e0| 1 plan9 ADC.S R0, R1, R2 +0010a1e0| 1 plan9 ADC R0, R1, R1 +0010b1e0| 1 plan9 ADC.S R0, R1, R1 +202ea1e0| 1 plan9 ADC R0>>$28, R1, R2 +002ea1e0| 1 plan9 ADC R0<<$28, R1, R2 +402ea1e0| 1 plan9 ADC R0->$28, R1, R2 +602ea1e0| 1 plan9 ADC R0@>$28, R1, R2 +202eb1e0| 1 plan9 ADC.S R0>>$28, R1, R2 +002eb1e0| 1 plan9 ADC.S R0<<$28, R1, R2 +402eb1e0| 1 plan9 ADC.S R0->$28, R1, R2 +602eb1e0| 1 plan9 ADC.S R0@>$28, R1, R2 +001ea1e0| 1 plan9 ADC R0<<$28, R1, R1 +201ea1e0| 1 plan9 ADC R0>>$28, R1, R1 +401ea1e0| 1 plan9 ADC R0->$28, R1, R1 +601ea1e0| 1 plan9 ADC R0@>$28, R1, R1 +001eb1e0| 1 plan9 ADC.S R0<<$28, R1, R1 +201eb1e0| 1 plan9 ADC.S R0>>$28, R1, R1 +401eb1e0| 1 plan9 ADC.S R0->$28, R1, R1 +601eb1e0| 1 plan9 ADC.S R0@>$28, R1, R1 +1031a2e0| 1 plan9 ADC R0<>R1, R2, R3 +5031a2e0| 1 plan9 ADC R0->R1, R2, R3 +7031a2e0| 1 plan9 ADC R0@>R1, R2, R3 +1031b2e0| 1 plan9 ADC.S R0<>R1, R2, R3 +5031b2e0| 1 plan9 ADC.S R0->R1, R2, R3 +7031b2e0| 1 plan9 ADC.S R0@>R1, R2, R3 +1021a2e0| 1 plan9 ADC R0<>R1, R2, R2 +5021a2e0| 1 plan9 ADC R0->R1, R2, R2 +7021a2e0| 1 plan9 ADC R0@>R1, R2, R2 +1021b2e0| 1 plan9 ADC.S R0<>R1, R2, R2 +5021b2e0| 1 plan9 ADC.S R0->R1, R2, R2 +7021b2e0| 1 plan9 ADC.S R0@>R1, R2, R2 +ff0037e3| 1 plan9 TEQ $255, R7 +ff0439e3| 1 plan9 TEQ $4278190080, R9 +090f37e1| 1 plan9 TEQ R9<<$30, R7 +290f37e1| 1 plan9 TEQ R9>>$30, R7 +490f37e1| 1 plan9 TEQ R9->$30, R7 +690f37e1| 1 plan9 TEQ R9@>$30, R7 +190837e1| 1 plan9 TEQ R9<>R8, R7 +590837e1| 1 plan9 TEQ R9->R8, R7 +790837e1| 1 plan9 TEQ R9@>R8, R7 +ff0017e3| 1 plan9 TST $255, R7 +ff0419e3| 1 plan9 TST $4278190080, R9 +090f17e1| 1 plan9 TST R9<<$30, R7 +290f17e1| 1 plan9 TST R9>>$30, R7 +490f17e1| 1 plan9 TST R9->$30, R7 +690f17e1| 1 plan9 TST R9@>$30, R7 +190817e1| 1 plan9 TST R9<>R8, R7 +590817e1| 1 plan9 TST R9->R8, R7 +790817e1| 1 plan9 TST R9@>R8, R7 +ff0057e3| 1 plan9 CMP $255, R7 +ff0459e3| 1 plan9 CMP $4278190080, R9 +090f57e1| 1 plan9 CMP R9<<$30, R7 +290f57e1| 1 plan9 CMP R9>>$30, R7 +490f57e1| 1 plan9 CMP R9->$30, R7 +690f57e1| 1 plan9 CMP R9@>$30, R7 +190857e1| 1 plan9 CMP R9<>R8, R7 +590857e1| 1 plan9 CMP R9->R8, R7 +790857e1| 1 plan9 CMP R9@>R8, R7 +ff0077e3| 1 plan9 CMN $255, R7 +ff0479e3| 1 plan9 CMN $4278190080, R9 +090f77e1| 1 plan9 CMN R9<<$30, R7 +290f77e1| 1 plan9 CMN R9>>$30, R7 +490f77e1| 1 plan9 CMN R9->$30, R7 +690f77e1| 1 plan9 CMN R9@>$30, R7 +190877e1| 1 plan9 CMN R9<>R8, R7 +590877e1| 1 plan9 CMN R9->R8, R7 +790877e1| 1 plan9 CMN R9@>R8, R7 +0c00000a| 1 plan9 B.EQ 0x38 +0b00001a| 1 plan9 B.NE 0x34 +0a00002a| 1 plan9 B.CS 0x30 +0900003a| 1 plan9 B.CC 0x2c +0800004a| 1 plan9 B.MI 0x28 +0700005a| 1 plan9 B.PL 0x24 +0600006a| 1 plan9 B.VS 0x20 +0500007a| 1 plan9 B.VC 0x1c +0400008a| 1 plan9 B.HI 0x18 +0300009a| 1 plan9 B.LS 0x14 +020000aa| 1 plan9 B.GE 0x10 +010000ba| 1 plan9 B.LT 0xc +000000ca| 1 plan9 B.GT 0x8 +ffffffda| 1 plan9 B.LE 0x4 +fdffffea| 1 plan9 B 0xfffffffc +fcffffea| 1 plan9 B 0xfffffff8 +fbffffea| 1 plan9 B 0xfffffff4 +faffffea| 1 plan9 B 0xfffffff0 +f9ffffea| 1 plan9 B 0xffffffec +feffffea| 1 plan9 B 0x0 +0c00000b| 1 plan9 BL.EQ 0x38 +0b00001b| 1 plan9 BL.NE 0x34 +0a00002b| 1 plan9 BL.CS 0x30 +0900003b| 1 plan9 BL.CC 0x2c +0800004b| 1 plan9 BL.MI 0x28 +0700005b| 1 plan9 BL.PL 0x24 +0600006b| 1 plan9 BL.VS 0x20 +0500007b| 1 plan9 BL.VC 0x1c +0400008b| 1 plan9 BL.HI 0x18 +0300009b| 1 plan9 BL.LS 0x14 +020000ab| 1 plan9 BL.GE 0x10 +010000bb| 1 plan9 BL.LT 0xc +000000cb| 1 plan9 BL.GT 0x8 +ffffffdb| 1 plan9 BL.LE 0x4 +fdffffeb| 1 plan9 BL 0xfffffffc +fcffffeb| 1 plan9 BL 0xfffffff8 +fbffffeb| 1 plan9 BL 0xfffffff4 +faffffeb| 1 plan9 BL 0xfffffff0 +f9ffffeb| 1 plan9 BL 0xffffffec +feffffeb| 1 plan9 BL 0x0 +ff10c0e3| 1 plan9 BIC $255, R0, R1 +ff14c0e3| 1 plan9 BIC $4278190080, R0, R1 +ff10d0e3| 1 plan9 BIC.S $255, R0, R1 +ff14d0e3| 1 plan9 BIC.S $4278190080, R0, R1 +ff00c0e3| 1 plan9 BIC $255, R0, R0 +ff04c0e3| 1 plan9 BIC $4278190080, R0, R0 +ff00d0e3| 1 plan9 BIC.S $255, R0, R0 +ff04d0e3| 1 plan9 BIC.S $4278190080, R0, R0 +0020c1e1| 1 plan9 BIC R0, R1, R2 +0020d1e1| 1 plan9 BIC.S R0, R1, R2 +0010c1e1| 1 plan9 BIC R0, R1, R1 +0010d1e1| 1 plan9 BIC.S R0, R1, R1 +202ec1e1| 1 plan9 BIC R0>>$28, R1, R2 +002ec1e1| 1 plan9 BIC R0<<$28, R1, R2 +402ec1e1| 1 plan9 BIC R0->$28, R1, R2 +602ec1e1| 1 plan9 BIC R0@>$28, R1, R2 +202ed1e1| 1 plan9 BIC.S R0>>$28, R1, R2 +002ed1e1| 1 plan9 BIC.S R0<<$28, R1, R2 +402ed1e1| 1 plan9 BIC.S R0->$28, R1, R2 +602ed1e1| 1 plan9 BIC.S R0@>$28, R1, R2 +001ec1e1| 1 plan9 BIC R0<<$28, R1, R1 +201ec1e1| 1 plan9 BIC R0>>$28, R1, R1 +401ec1e1| 1 plan9 BIC R0->$28, R1, R1 +601ec1e1| 1 plan9 BIC R0@>$28, R1, R1 +001ed1e1| 1 plan9 BIC.S R0<<$28, R1, R1 +201ed1e1| 1 plan9 BIC.S R0>>$28, R1, R1 +401ed1e1| 1 plan9 BIC.S R0->$28, R1, R1 +601ed1e1| 1 plan9 BIC.S R0@>$28, R1, R1 +1031c2e1| 1 plan9 BIC R0<>R1, R2, R3 +5031c2e1| 1 plan9 BIC R0->R1, R2, R3 +7031c2e1| 1 plan9 BIC R0@>R1, R2, R3 +1031d2e1| 1 plan9 BIC.S R0<>R1, R2, R3 +5031d2e1| 1 plan9 BIC.S R0->R1, R2, R3 +7031d2e1| 1 plan9 BIC.S R0@>R1, R2, R3 +1021c2e1| 1 plan9 BIC R0<>R1, R2, R2 +5021c2e1| 1 plan9 BIC R0->R1, R2, R2 +7021c2e1| 1 plan9 BIC R0@>R1, R2, R2 +1021d2e1| 1 plan9 BIC.S R0<>R1, R2, R2 +5021d2e1| 1 plan9 BIC.S R0->R1, R2, R2 +7021d2e1| 1 plan9 BIC.S R0@>R1, R2, R2 +2567a0e1| 1 plan9 LSR $14, R5, R6 +a567a0e1| 1 plan9 LSR $15, R5, R6 +256fa0e1| 1 plan9 LSR $30, R5, R6 +a56fa0e1| 1 plan9 LSR $31, R5, R6 +2567b0e1| 1 plan9 LSR.S $14, R5, R6 +a567b0e1| 1 plan9 LSR.S $15, R5, R6 +256fb0e1| 1 plan9 LSR.S $30, R5, R6 +a56fb0e1| 1 plan9 LSR.S $31, R5, R6 +2557a0e1| 1 plan9 LSR $14, R5, R5 +a557a0e1| 1 plan9 LSR $15, R5, R5 +255fa0e1| 1 plan9 LSR $30, R5, R5 +a55fa0e1| 1 plan9 LSR $31, R5, R5 +2557b0e1| 1 plan9 LSR.S $14, R5, R5 +a557b0e1| 1 plan9 LSR.S $15, R5, R5 +255fb0e1| 1 plan9 LSR.S $30, R5, R5 +a55fb0e1| 1 plan9 LSR.S $31, R5, R5 +3675a0e1| 1 plan9 LSR R5, R6, R7 +3675b0e1| 1 plan9 LSR.S R5, R6, R7 +3775a0e1| 1 plan9 LSR R5, R7, R7 +3775b0e1| 1 plan9 LSR.S R5, R7, R7 +4567a0e1| 1 plan9 ASR $14, R5, R6 +c567a0e1| 1 plan9 ASR $15, R5, R6 +456fa0e1| 1 plan9 ASR $30, R5, R6 +c56fa0e1| 1 plan9 ASR $31, R5, R6 +4567b0e1| 1 plan9 ASR.S $14, R5, R6 +c567b0e1| 1 plan9 ASR.S $15, R5, R6 +456fb0e1| 1 plan9 ASR.S $30, R5, R6 +c56fb0e1| 1 plan9 ASR.S $31, R5, R6 +4557a0e1| 1 plan9 ASR $14, R5, R5 +c557a0e1| 1 plan9 ASR $15, R5, R5 +455fa0e1| 1 plan9 ASR $30, R5, R5 +c55fa0e1| 1 plan9 ASR $31, R5, R5 +4557b0e1| 1 plan9 ASR.S $14, R5, R5 +c557b0e1| 1 plan9 ASR.S $15, R5, R5 +455fb0e1| 1 plan9 ASR.S $30, R5, R5 +c55fb0e1| 1 plan9 ASR.S $31, R5, R5 +5675a0e1| 1 plan9 ASR R5, R6, R7 +5675b0e1| 1 plan9 ASR.S R5, R6, R7 +5775a0e1| 1 plan9 ASR R5, R7, R7 +5775b0e1| 1 plan9 ASR.S R5, R7, R7 +0567a0e1| 1 plan9 LSL $14, R5, R6 +8567a0e1| 1 plan9 LSL $15, R5, R6 +056fa0e1| 1 plan9 LSL $30, R5, R6 +856fa0e1| 1 plan9 LSL $31, R5, R6 +0567b0e1| 1 plan9 LSL.S $14, R5, R6 +8567b0e1| 1 plan9 LSL.S $15, R5, R6 +056fb0e1| 1 plan9 LSL.S $30, R5, R6 +856fb0e1| 1 plan9 LSL.S $31, R5, R6 +0557a0e1| 1 plan9 LSL $14, R5, R5 +8557a0e1| 1 plan9 LSL $15, R5, R5 +055fa0e1| 1 plan9 LSL $30, R5, R5 +855fa0e1| 1 plan9 LSL $31, R5, R5 +0557b0e1| 1 plan9 LSL.S $14, R5, R5 +8557b0e1| 1 plan9 LSL.S $15, R5, R5 +055fb0e1| 1 plan9 LSL.S $30, R5, R5 +855fb0e1| 1 plan9 LSL.S $31, R5, R5 +1675a0e1| 1 plan9 LSL R5, R6, R7 +1675b0e1| 1 plan9 LSL.S R5, R6, R7 +1775a0e1| 1 plan9 LSL R5, R7, R7 +1775b0e1| 1 plan9 LSL.S R5, R7, R7 +c23124e1| 1 plan9 SMLAWT R1, R2, R3, R4 +823124e1| 1 plan9 SMLAWB R1, R2, R3, R4 +923164e0| 1 plan9 MLS R1, R2, R3, R4 +923124e0| 1 plan9 MLA R1, R2, R3, R4 +923134e0| 1 plan9 MLA.S R1, R2, R3, R4 +123154e7| 1 plan9 SMMLA R1, R2, R3, R4 +d23154e7| 1 plan9 SMMLS R1, R2, R3, R4 +823104e1| 1 plan9 SMLABB R1, R2, R3, R4 +a23104e1| 1 plan9 SMLATB R1, R2, R3, R4 +c23104e1| 1 plan9 SMLABT R1, R2, R3, R4 +e23104e1| 1 plan9 SMLATT R1, R2, R3, R4 +123104e7| 1 plan9 SMLAD R1, R2, R3, R4 +323104e7| 1 plan9 SMLAD.X R1, R2, R3, R4 +523104e7| 1 plan9 SMLSD R1, R2, R3, R4 +723104e7| 1 plan9 SMLSD.X R1, R2, R3, R4 +9231e4e0| 1 plan9 SMLAL R1, R2, R4, R3 +9231f4e0| 1 plan9 SMLAL.S R1, R2, R4, R3 +123144e7| 1 plan9 SMLALD R1, R2, R4, R3 +323144e7| 1 plan9 SMLALD.X R1, R2, R4, R3 +523144e7| 1 plan9 SMLSLD R1, R2, R4, R3 +723144e7| 1 plan9 SMLSLD.X R1, R2, R4, R3 +9231a4e0| 1 plan9 UMLAL R1, R2, R4, R3 +923144e0| 1 plan9 UMAAL R1, R2, R4, R3 +9231b4e0| 1 plan9 UMLAL.S R1, R2, R4, R3 +930204e0| 1 plan9 MUL R2, R3, R4 +920404e0| 1 plan9 MUL R4, R2, R4 +930214e0| 1 plan9 MUL.S R2, R3, R4 +920414e0| 1 plan9 MUL.S R4, R2, R4 +960507e0| 1 plan9 MUL R5, R6, R7 +950707e0| 1 plan9 MUL R7, R5, R7 +960517e0| 1 plan9 MUL.S R5, R6, R7 +950717e0| 1 plan9 MUL.S R7, R5, R7 +923184e0| 1 plan9 UMULL R1, R2, R4, R3 +923194e0| 1 plan9 UMULL.S R1, R2, R4, R3 +9231c4e0| 1 plan9 SMULL R1, R2, R4, R3 +9231d4e0| 1 plan9 SMULL.S R1, R2, R4, R3 +12f153e7| 1 plan9 SMMUL R1, R2, R3 +820163e1| 1 plan9 SMULBB R1, R2, R3 +a20163e1| 1 plan9 SMULTB R1, R2, R3 +c20163e1| 1 plan9 SMULBT R1, R2, R3 +e20163e1| 1 plan9 SMULTT R1, R2, R3 +a20123e1| 1 plan9 SMULWB R1, R2, R3 +e20123e1| 1 plan9 SMULWT R1, R2, R3 +12f103e7| 1 plan9 SMUAD R1, R2, R3 +32f103e7| 1 plan9 SMUAD.X R1, R2, R3 +52f103e7| 1 plan9 SMUSD R1, R2, R3 +72f103e7| 1 plan9 SMUSD.X R1, R2, R3 +312fbfe6| 1 plan9 REV R1, R2 +b12fbfe6| 1 plan9 REV16 R1, R2 +b12fffe6| 1 plan9 REVSH R1, R2 +312fffe6| 1 plan9 RBIT R1, R2 +112f6fe1| 1 plan9 CLZ R1, R2 +f0ffd6f5| 1 gnu pld [r6, #4080] +f0ff59f5| 1 gnu pld [r9, #-4080] +f0ff96f5| 1 gnu pldw [r6, #4080] +f0ff19f5| 1 gnu pldw [r9, #-4080] +f0ffdff5| 1 gnu pld [pc, #4080] +f0ff5ff5| 1 gnu pld [pc, #-4080] +00f0d2f7| 1 gnu pld [r2, r0] +00f052f7| 1 gnu pld [r2, -r0] +00f092f7| 1 gnu pldw [r2, r0] +00f012f7| 1 gnu pldw [r2, -r0] +80f0d2f7| 1 gnu pld [r2, r0, lsl #1] +80f052f7| 1 gnu pld [r2, -r0, lsl #1] +a0f0d2f7| 1 gnu pld [r2, r0, lsr #1] +a0f052f7| 1 gnu pld [r2, -r0, lsr #1] +c0f0d2f7| 1 gnu pld [r2, r0, asr #1] +c0f052f7| 1 gnu pld [r2, -r0, asr #1] +e0f0d2f7| 1 gnu pld [r2, r0, ror #1] +e0f052f7| 1 gnu pld [r2, -r0, ror #1] +80f092f7| 1 gnu pldw [r2, r0, lsl #1] +80f012f7| 1 gnu pldw [r2, -r0, lsl #1] +a0f092f7| 1 gnu pldw [r2, r0, lsr #1] +a0f012f7| 1 gnu pldw [r2, -r0, lsr #1] +c0f092f7| 1 gnu pldw [r2, r0, asr #1] +c0f012f7| 1 gnu pldw [r2, -r0, asr #1] +e0f092f7| 1 gnu pldw [r2, r0, ror #1] +e0f012f7| 1 gnu pldw [r2, -r0, ror #1] +f0ffd2f4| 1 gnu pli [r2, #4080] +f0ff52f4| 1 gnu pli [r2, #-4080] +82f0d3f6| 1 gnu pli [r3, r2, lsl #1] +82f053f6| 1 gnu pli [r3, -r2, lsl #1] +a2f0d3f6| 1 gnu pli [r3, r2, lsr #1] +a2f053f6| 1 gnu pli [r3, -r2, lsr #1] +c2f0d3f6| 1 gnu pli [r3, r2, asr #1] +c2f053f6| 1 gnu pli [r3, -r2, asr #1] +e2f0d3f6| 1 gnu pli [r3, r2, ror #1] +e2f053f6| 1 gnu pli [r3, -r2, ror #1] +939007e1| 1 gnu swp r9, r3, [r7] +948042e1| 1 gnu swpb r8, r4, [r2] +000000ef| 1 plan9 SVC $0 +ffff00ef| 1 plan9 SVC $65535 +ff10e0e3| 1 plan9 MVN $255, R1 +ff14e0e3| 1 plan9 MVN $4278190080, R1 +ff10f0e3| 1 plan9 MVN.S $255, R1 +ff14f0e3| 1 plan9 MVN.S $4278190080, R1 +097fe0e1| 1 plan9 MVN R9<<$30, R7 +297fe0e1| 1 plan9 MVN R9>>$30, R7 +497fe0e1| 1 plan9 MVN R9->$30, R7 +697fe0e1| 1 plan9 MVN R9@>$30, R7 +097ff0e1| 1 plan9 MVN.S R9<<$30, R7 +297ff0e1| 1 plan9 MVN.S R9>>$30, R7 +497ff0e1| 1 plan9 MVN.S R9->$30, R7 +697ff0e1| 1 plan9 MVN.S R9@>$30, R7 +1978e0e1| 1 plan9 MVN R9<>R8, R7 +5978e0e1| 1 plan9 MVN R9->R8, R7 +7978e0e1| 1 plan9 MVN R9@>R8, R7 +1978f0e1| 1 plan9 MVN.S R9<>R8, R7 +5978f0e1| 1 plan9 MVN.S R9->R8, R7 +7978f0e1| 1 plan9 MVN.S R9@>R8, R7 +550081e8| 1 plan9 STM [R0,R2,R4,R6], R1 +5f0f81e8| 1 plan9 STM [R0-R4,R6,R8-R11], R1 +5500a1e8| 1 plan9 STM [R0,R2,R4,R6], R1! +5f0fa1e8| 1 plan9 STM [R0-R4,R6,R8-R11], R1! +550091e8| 1 plan9 LDM [R0,R2,R4,R6], R1 +5f0f91e8| 1 plan9 LDM [R0-R4,R6,R8-R11], R1 +5500b1e8| 1 plan9 LDM [R0,R2,R4,R6], R1! +5f0fb1e8| 1 plan9 LDM [R0-R4,R6,R8-R11], R1! +550001e8| 1 plan9 STMDA [R0,R2,R4,R6], R1 +5f0f01e8| 1 plan9 STMDA [R0-R4,R6,R8-R11], R1 +550021e8| 1 plan9 STMDA [R0,R2,R4,R6], R1! +5f0f21e8| 1 plan9 STMDA [R0-R4,R6,R8-R11], R1! +550011e8| 1 plan9 LDMDA [R0,R2,R4,R6], R1 +5f0f11e8| 1 plan9 LDMDA [R0-R4,R6,R8-R11], R1 +550031e8| 1 plan9 LDMDA [R0,R2,R4,R6], R1! +5f0f31e8| 1 plan9 LDMDA [R0-R4,R6,R8-R11], R1! +550001e9| 1 plan9 STMDB [R0,R2,R4,R6], R1 +5f0f01e9| 1 plan9 STMDB [R0-R4,R6,R8-R11], R1 +550021e9| 1 plan9 STMDB [R0,R2,R4,R6], R1! +5f0f21e9| 1 plan9 STMDB [R0-R4,R6,R8-R11], R1! +550011e9| 1 plan9 LDMDB [R0,R2,R4,R6], R1 +5f0f11e9| 1 plan9 LDMDB [R0-R4,R6,R8-R11], R1 +550031e9| 1 plan9 LDMDB [R0,R2,R4,R6], R1! +5f0f31e9| 1 plan9 LDMDB [R0-R4,R6,R8-R11], R1! +55008ae9| 1 plan9 STMIB [R0,R2,R4,R6], R10 +5f0f8ae9| 1 plan9 STMIB [R0-R4,R6,R8-R11], R10 +5500aae9| 1 plan9 STMIB [R0,R2,R4,R6], R10! +5f0faae9| 1 plan9 STMIB [R0-R4,R6,R8-R11], R10! +55009ae9| 1 plan9 LDMIB [R0,R2,R4,R6], R10 +5f0f9ae9| 1 plan9 LDMIB [R0-R4,R6,R8-R11], R10 +5500bae9| 1 plan9 LDMIB [R0,R2,R4,R6], R10! +5f0fbae9| 1 plan9 LDMIB [R0-R4,R6,R8-R11], R10! +0340a0e1| 1 plan9 MOVW R3, R4 +0920a0e1| 1 plan9 MOVW R9, R2 +ff90a0e3| 1 plan9 MOVW $255, R9 +ff94a0e3| 1 plan9 MOVW $4278190080, R9 +aaaa0a13| 1 plan9 MOVW.NE $43690, R10 +aaaa4a03| 1 plan9 MOVT.EQ $43690, R10 +5110e0e3| 1 plan9 MVN $81, R1 +001082e5| 1 plan9 MOVW R1, (R2) +001082e4| 1 plan9 MOVW.P R1, (R2) +0010a2e5| 1 plan9 MOVW.W R1, (R2) +201082e5| 1 plan9 MOVW R1, 0x20(R2) +201082e4| 1 plan9 MOVW.P R1, 0x20(R2) +2010a2e5| 1 plan9 MOVW.W R1, 0x20(R2) +201002e5| 1 plan9 MOVW R1, -0x20(R2) +201002e4| 1 plan9 MOVW.P R1, -0x20(R2) +201022e5| 1 plan9 MOVW.W R1, -0x20(R2) +001092e5| 1 plan9 MOVW (R2), R1 +001092e4| 1 plan9 MOVW.P (R2), R1 +0010b2e5| 1 plan9 MOVW.W (R2), R1 +201092e5| 1 plan9 MOVW 0x20(R2), R1 +201092e4| 1 plan9 MOVW.P 0x20(R2), R1 +2010b2e5| 1 plan9 MOVW.W 0x20(R2), R1 +201012e5| 1 plan9 MOVW -0x20(R2), R1 +201012e4| 1 plan9 MOVW.P -0x20(R2), R1 +201032e5| 1 plan9 MOVW.W -0x20(R2), R1 +00100fe1| 1 plan9 MRS APSR, R1 +fef02ce3| 1 plan9 MSR $254, APSR +fff42ce3| 1 plan9 MSR $4278190080, APSR +05f02c01| 1 plan9 MSR.EQ R5, APSR +09f02c11| 1 plan9 MSR.NE R9, APSR +109af1ee| 1 plan9 VMRS FPSCR, R9 +10aaf1ee| 1 plan9 VMRS FPSCR, R10 +109ae1ee| 1 plan9 VMSR R9, FPSCR +10aae1ee| 1 plan9 VMSR R10, FPSCR +202e91e7| 1 plan9 MOVW (R1)(R0>>28), R2 +002e91e7| 1 plan9 MOVW (R1)(R0<<28), R2 +402e91e7| 1 plan9 MOVW (R1)(R0->28), R2 +602e91e7| 1 plan9 MOVW (R1)(R0@>28), R2 +202e11e7| 1 plan9 MOVW.U (R1)(R0>>28), R2 +002e11e7| 1 plan9 MOVW.U (R1)(R0<<28), R2 +402e11e7| 1 plan9 MOVW.U (R1)(R0->28), R2 +602e11e7| 1 plan9 MOVW.U (R1)(R0@>28), R2 +202eb1e7| 1 plan9 MOVW.W (R1)(R0>>28), R2 +002eb1e7| 1 plan9 MOVW.W (R1)(R0<<28), R2 +402eb1e7| 1 plan9 MOVW.W (R1)(R0->28), R2 +602eb1e7| 1 plan9 MOVW.W (R1)(R0@>28), R2 +202e9ae6| 1 plan9 MOVW.P (R10)(R0>>28), R2 +002e9ae6| 1 plan9 MOVW.P (R10)(R0<<28), R2 +402e9ae6| 1 plan9 MOVW.P (R10)(R0->28), R2 +602e9ae6| 1 plan9 MOVW.P (R10)(R0@>28), R2 +202e81e7| 1 plan9 MOVW R2, (R1)(R0>>28) +002e81e7| 1 plan9 MOVW R2, (R1)(R0<<28) +402e81e7| 1 plan9 MOVW R2, (R1)(R0->28) +602e81e7| 1 plan9 MOVW R2, (R1)(R0@>28) +202e01e7| 1 plan9 MOVW.U R2, (R1)(R0>>28) +002e01e7| 1 plan9 MOVW.U R2, (R1)(R0<<28) +402e01e7| 1 plan9 MOVW.U R2, (R1)(R0->28) +602e01e7| 1 plan9 MOVW.U R2, (R1)(R0@>28) +202ea1e7| 1 plan9 MOVW.W R2, (R1)(R0>>28) +002ea1e7| 1 plan9 MOVW.W R2, (R1)(R0<<28) +402ea1e7| 1 plan9 MOVW.W R2, (R1)(R0->28) +602ea1e7| 1 plan9 MOVW.W R2, (R1)(R0@>28) +202e85e6| 1 plan9 MOVW.P R2, (R5)(R0>>28) +002e85e6| 1 plan9 MOVW.P R2, (R5)(R0<<28) +402e85e6| 1 plan9 MOVW.P R2, (R5)(R0->28) +602e85e6| 1 plan9 MOVW.P R2, (R5)(R0@>28) +0010c2e5| 1 plan9 MOVB R1, (R2) +0010c2e4| 1 plan9 MOVB.P R1, (R2) +0010e2e5| 1 plan9 MOVB.W R1, (R2) +2010c2e5| 1 plan9 MOVB R1, 0x20(R2) +2010c2e4| 1 plan9 MOVB.P R1, 0x20(R2) +2010e2e5| 1 plan9 MOVB.W R1, 0x20(R2) +201042e5| 1 plan9 MOVB R1, -0x20(R2) +201042e4| 1 plan9 MOVB.P R1, -0x20(R2) +201062e5| 1 plan9 MOVB.W R1, -0x20(R2) +d010d2e1| 1 plan9 MOVBS (R2), R1 +d010d2e0| 1 plan9 MOVBS.P (R2), R1 +d010f2e1| 1 plan9 MOVBS.W (R2), R1 +d012d2e1| 1 plan9 MOVBS 0x20(R2), R1 +d012d2e0| 1 plan9 MOVBS.P 0x20(R2), R1 +d012f2e1| 1 plan9 MOVBS.W 0x20(R2), R1 +d01252e1| 1 plan9 MOVBS -0x20(R2), R1 +d01252e0| 1 plan9 MOVBS.P -0x20(R2), R1 +d01272e1| 1 plan9 MOVBS.W -0x20(R2), R1 +0010d2e5| 1 plan9 MOVBU (R2), R1 +0010dfe5| 1 plan9 MOVBU (R15), R1 +0020dfe5| 1 plan9 MOVBU (R15), R2 +0010d2e4| 1 plan9 MOVBU.P (R2), R1 +0010f2e5| 1 plan9 MOVBU.W (R2), R1 +2010d2e5| 1 plan9 MOVBU 0x20(R2), R1 +2010d2e4| 1 plan9 MOVBU.P 0x20(R2), R1 +2010f2e5| 1 plan9 MOVBU.W 0x20(R2), R1 +201052e5| 1 plan9 MOVBU -0x20(R2), R1 +201052e4| 1 plan9 MOVBU.P -0x20(R2), R1 +201072e5| 1 plan9 MOVBU.W -0x20(R2), R1 +202ec1e7| 1 plan9 MOVB R2, (R1)(R0>>28) +002ec1e7| 1 plan9 MOVB R2, (R1)(R0<<28) +402ec1e7| 1 plan9 MOVB R2, (R1)(R0->28) +602ec1e7| 1 plan9 MOVB R2, (R1)(R0@>28) +202e41e7| 1 plan9 MOVB.U R2, (R1)(R0>>28) +002e41e7| 1 plan9 MOVB.U R2, (R1)(R0<<28) +402e41e7| 1 plan9 MOVB.U R2, (R1)(R0->28) +602e41e7| 1 plan9 MOVB.U R2, (R1)(R0@>28) +202ee1e7| 1 plan9 MOVB.W R2, (R1)(R0>>28) +002ee1e7| 1 plan9 MOVB.W R2, (R1)(R0<<28) +402ee1e7| 1 plan9 MOVB.W R2, (R1)(R0->28) +602ee1e7| 1 plan9 MOVB.W R2, (R1)(R0@>28) +202e61e7| 1 plan9 MOVB.W.U R2, (R1)(R0>>28) +002e61e7| 1 plan9 MOVB.W.U R2, (R1)(R0<<28) +402e61e7| 1 plan9 MOVB.W.U R2, (R1)(R0->28) +602e61e7| 1 plan9 MOVB.W.U R2, (R1)(R0@>28) +202ec5e6| 1 plan9 MOVB.P R2, (R5)(R0>>28) +002ec5e6| 1 plan9 MOVB.P R2, (R5)(R0<<28) +402ec5e6| 1 plan9 MOVB.P R2, (R5)(R0->28) +602ec5e6| 1 plan9 MOVB.P R2, (R5)(R0@>28) +202ed1e7| 1 plan9 MOVBU (R1)(R0>>28), R2 +002ed1e7| 1 plan9 MOVBU (R1)(R0<<28), R2 +402ed1e7| 1 plan9 MOVBU (R1)(R0->28), R2 +602ed1e7| 1 plan9 MOVBU (R1)(R0@>28), R2 +202e51e7| 1 plan9 MOVBU.U (R1)(R0>>28), R2 +002e51e7| 1 plan9 MOVBU.U (R1)(R0<<28), R2 +402e51e7| 1 plan9 MOVBU.U (R1)(R0->28), R2 +602e51e7| 1 plan9 MOVBU.U (R1)(R0@>28), R2 +202ef1e7| 1 plan9 MOVBU.W (R1)(R0>>28), R2 +002ef1e7| 1 plan9 MOVBU.W (R1)(R0<<28), R2 +402ef1e7| 1 plan9 MOVBU.W (R1)(R0->28), R2 +602ef1e7| 1 plan9 MOVBU.W (R1)(R0@>28), R2 +202e71e7| 1 plan9 MOVBU.W.U (R1)(R0>>28), R2 +002e71e7| 1 plan9 MOVBU.W.U (R1)(R0<<28), R2 +402e71e7| 1 plan9 MOVBU.W.U (R1)(R0->28), R2 +602e71e7| 1 plan9 MOVBU.W.U (R1)(R0@>28), R2 +202edae6| 1 plan9 MOVBU.P (R10)(R0>>28), R2 +002edae6| 1 plan9 MOVBU.P (R10)(R0<<28), R2 +402edae6| 1 plan9 MOVBU.P (R10)(R0->28), R2 +602edae6| 1 plan9 MOVBU.P (R10)(R0@>28), R2 +d02091e1| 1 plan9 MOVBS (R1)(R0), R2 +d02011e1| 1 plan9 MOVBS.U (R1)(R0), R2 +d020b1e1| 1 plan9 MOVBS.W (R1)(R0), R2 +d02091e0| 1 plan9 MOVBS.P (R1)(R0), R2 +b040c3e1| 1 plan9 MOVH R4, (R3) +b032c4e1| 1 plan9 MOVH R3, 0x20(R4) +b032e4e1| 1 plan9 MOVH.W R3, 0x20(R4) +b032c4e0| 1 plan9 MOVH.P R3, 0x20(R4) +b03244e1| 1 plan9 MOVH R3, -0x20(R4) +b03264e1| 1 plan9 MOVH.W R3, -0x20(R4) +b03244e0| 1 plan9 MOVH.P R3, -0x20(R4) +b080d9e1| 1 plan9 MOVHU (R9), R8 +b080f9e1| 1 plan9 MOVHU.W (R9), R8 +b080d9e0| 1 plan9 MOVHU.P (R9), R8 +f080d9e1| 1 plan9 MOVHS (R9), R8 +f080f9e1| 1 plan9 MOVHS.W (R9), R8 +f080d9e0| 1 plan9 MOVHS.P (R9), R8 +b282d9e1| 1 plan9 MOVHU 0x22(R9), R8 +b282f9e1| 1 plan9 MOVHU.W 0x22(R9), R8 +b282d9e0| 1 plan9 MOVHU.P 0x22(R9), R8 +f282d9e1| 1 plan9 MOVHS 0x22(R9), R8 +f282f9e1| 1 plan9 MOVHS.W 0x22(R9), R8 +f282d9e0| 1 plan9 MOVHS.P 0x22(R9), R8 +b48259e1| 1 plan9 MOVHU -0x24(R9), R8 +b48279e1| 1 plan9 MOVHU.W -0x24(R9), R8 +b48259e0| 1 plan9 MOVHU.P -0x24(R9), R8 +f48259e1| 1 plan9 MOVHS -0x24(R9), R8 +f48279e1| 1 plan9 MOVHS.W -0x24(R9), R8 +f48259e0| 1 plan9 MOVHS.P -0x24(R9), R8 +002a31ee| 1 plan9 VADD.F32 S0, S2, S4 +202a31ee| 1 plan9 VADD.F32 S1, S2, S4 +802a31ee| 1 plan9 VADD.F32 S0, S3, S4 +002a71ee| 1 plan9 VADD.F32 S0, S2, S5 +035b340e| 1 plan9 VADD.EQ.F64 D3, D4, D5 +002a321e| 1 plan9 VADD.NE.F32 S0, S4, S4 +035b35ee| 1 plan9 VADD.F64 D3, D5, D5 +402a31ee| 1 plan9 VSUB.F32 S0, S2, S4 +602a31ee| 1 plan9 VSUB.F32 S1, S2, S4 +c02a31ee| 1 plan9 VSUB.F32 S0, S3, S4 +402a71ee| 1 plan9 VSUB.F32 S0, S2, S5 +435b340e| 1 plan9 VSUB.EQ.F64 D3, D4, D5 +402a321e| 1 plan9 VSUB.NE.F32 S0, S4, S4 +435b35ee| 1 plan9 VSUB.F64 D3, D5, D5 +002a21ee| 1 plan9 VMUL.F32 S0, S2, S4 +202a21ee| 1 plan9 VMUL.F32 S1, S2, S4 +802a21ee| 1 plan9 VMUL.F32 S0, S3, S4 +002a61ee| 1 plan9 VMUL.F32 S0, S2, S5 +035b240e| 1 plan9 VMUL.EQ.F64 D3, D4, D5 +002a221e| 1 plan9 VMUL.NE.F32 S0, S4, S4 +035b25ee| 1 plan9 VMUL.F64 D3, D5, D5 +002a81ee| 1 plan9 VDIV.F32 S0, S2, S4 +202a81ee| 1 plan9 VDIV.F32 S1, S2, S4 +802a81ee| 1 plan9 VDIV.F32 S0, S3, S4 +002ac1ee| 1 plan9 VDIV.F32 S0, S2, S5 +035b840e| 1 plan9 VDIV.EQ.F64 D3, D4, D5 +002a821e| 1 plan9 VDIV.NE.F32 S0, S4, S4 +035b85ee| 1 plan9 VDIV.F64 D3, D5, D5 +401ab1ee| 1 plan9 VNEG.F32 S0, S2 +601ab1ee| 1 plan9 VNEG.F32 S1, S2 +401af1ee| 1 plan9 VNEG.F32 S0, S3 +445bb1ee| 1 plan9 VNEG.F64 D4, D5 +c01ab0ee| 1 plan9 VABS.F32 S0, S2 +e01ab0ee| 1 plan9 VABS.F32 S1, S2 +c01af0ee| 1 plan9 VABS.F32 S0, S3 +c45bb0ee| 1 plan9 VABS.F64 D4, D5 +c01ab1ee| 1 plan9 VSQRT.F32 S0, S2 +e01ab1ee| 1 plan9 VSQRT.F32 S1, S2 +c01af1ee| 1 plan9 VSQRT.F32 S0, S3 +c45bb1ee| 1 plan9 VSQRT.F64 D4, D5 +c01ab7ee| 1 gnu vcvt.f64.f32 d1, s0 +c45bb7ee| 1 gnu vcvt.f32.f64 s10, d4 +9f9f98e1| 1 gnu ldrex r9, [r8] +9f9fd8e1| 1 gnu ldrexb r9, [r8] +9f9ff8e1| 1 gnu ldrexh r9, [r8] +9fcfbbe1| 1 gnu ldrexd ip, [fp] +935f84e1| 1 gnu strex r5, r3, [r4] +935fc4e1| 1 gnu strexb r5, r3, [r4] +935fe4e1| 1 gnu strexh r5, r3, [r4] +98afa9e1| 1 gnu strexd sl, r8, [r9] +104b08ee| 1 gnu vmov.32 d8[0], r4 +108b14ee| 1 gnu vmov.32 r8, d4[0] +445ab0ee| 1 gnu vmov.f32 s10, s8 +467bb0ee| 1 gnu vmov.f64 d7, d6 +c68abdee| 1 gnu vcvt.s32.f32 s16, s12 +c68abcee| 1 gnu vcvt.u32.f32 s16, s12 +c68bbdee| 1 gnu vcvt.s32.f64 s16, d6 +c68bbcee| 1 gnu vcvt.u32.f64 s16, d6 +c68ab8ee| 1 gnu vcvt.f32.s32 s16, s12 +468ab8ee| 1 gnu vcvt.f32.u32 s16, s12 +c68bb8ee| 1 gnu vcvt.f64.s32 d8, s12 +468bb8ee| 1 gnu vcvt.f64.u32 d8, s12 +000000ea| 1 plan9 B 0x8 +feffffea| 1 plan9 B 0x0 +fcffffea| 1 plan9 B 0xfffffff8 +1f90cfe7| 1 plan9 BFC $16, $0, R9 +9fb4dee7| 1 plan9 BFC $22, $9, R11 +1790cfe7| 1 plan9 BFI $16, $0, R7, R9 +98b4dee7| 1 plan9 BFI $22, $9, R8, R11 +742321e1| 1 plan9 BKPT $4660 +000000eb| 1 plan9 BL 0x8 +feffffeb| 1 plan9 BL 0x0 +fcffffeb| 1 plan9 BL 0xfffffff8 +000000fa| 1 plan9 BLX 0x8 +fefffffa| 1 plan9 BLX 0x0 +fcfffffa| 1 plan9 BLX 0xfffffff8 +33ff2fe1| 1 plan9 BLX R3 +13ff2fe1| 1 plan9 BX R3 +23ff2fe1| 1 plan9 BXJ R3 +1ff07ff5| 1 plan9 CLREX +f7f020e3| 1 gnu dbg #7 +58f07ff5| 1 gnu dmb #8 +49f07ff5| 1 gnu dsb #9 +62f07ff5| 1 gnu isb #2 +009a94ed| 1 plan9 MOVF (R4), F9 +009ad4ed| 1 plan9 MOVF (R4), S19 +009b940d| 1 plan9 MOVD.EQ (R4), F9 +003a9a1d| 1 plan9 MOVF.NE (R10), F3 +003ada1d| 1 plan9 MOVF.NE (R10), S7 +003b9aed| 1 plan9 MOVD (R10), F3 +089a93ed| 1 plan9 MOVF 0x20(R3), F9 +089ad3ed| 1 plan9 MOVF 0x20(R3), S19 +089b940d| 1 plan9 MOVD.EQ 0x20(R4), F9 +083a1a1d| 1 plan9 MOVF.NE -0x20(R10), F3 +083a5a1d| 1 plan9 MOVF.NE -0x20(R10), S7 +083b1aed| 1 plan9 MOVD -0x20(R10), F3 +009a84ed| 1 plan9 MOVF F9, (R4) +009ac4ed| 1 plan9 MOVF S19, (R4) +009b840d| 1 plan9 MOVD.EQ F9, (R4) +003a8a1d| 1 plan9 MOVF.NE F3, (R10) +003aca1d| 1 plan9 MOVF.NE S7, (R10) +003b8aed| 1 plan9 MOVD F3, (R10) +089a83ed| 1 plan9 MOVF F9, 0x20(R3) +089ac3ed| 1 plan9 MOVF S19, 0x20(R3) +089b840d| 1 plan9 MOVD.EQ F9, 0x20(R4) +083a0a1d| 1 plan9 MOVF.NE F3, -0x20(R10) +083a4a1d| 1 plan9 MOVF.NE S7, -0x20(R10) +083b0aed| 1 plan9 MOVD F3, -0x20(R10) +d060c8e1| 1 gnu ldrd r6, [r8] +d06048e1| 1 gnu ldrd r6, [r8] +d060e8e1| 1 gnu ldrd r6, [r8, #0]! +d06068e1| 1 gnu ldrd r6, [r8, #0]! +d060c8e0| 1 gnu ldrd r6, [r8], #0 +d06048e0| 1 gnu ldrd r6, [r8], #0 +d062c8e1| 1 gnu ldrd r6, [r8, #32] +d06248e1| 1 gnu ldrd r6, [r8, #-32] +d062e8e1| 1 gnu ldrd r6, [r8, #32]! +d06268e1| 1 gnu ldrd r6, [r8, #-32]! +d062c8e0| 1 gnu ldrd r6, [r8], #32 +d06248e0| 1 gnu ldrd r6, [r8], #-32 +d24089e1| 1 gnu ldrd r4, [r9, r2] +d240a9e1| 1 gnu ldrd r4, [r9, r2]! +d24009e1| 1 gnu ldrd r4, [r9, -r2] +d24029e1| 1 gnu ldrd r4, [r9, -r2]! +f060c8e1| 1 gnu strd r6, [r8] +f06048e1| 1 gnu strd r6, [r8] +f060e8e1| 1 gnu strd r6, [r8, #0]! +f06068e1| 1 gnu strd r6, [r8, #0]! +f060c8e0| 1 gnu strd r6, [r8], #0 +f06048e0| 1 gnu strd r6, [r8], #0 +f062c8e1| 1 gnu strd r6, [r8, #32] +f06248e1| 1 gnu strd r6, [r8, #-32] +f062e8e1| 1 gnu strd r6, [r8, #32]! +f06268e1| 1 gnu strd r6, [r8, #-32]! +f062c8e0| 1 gnu strd r6, [r8], #32 +f06248e0| 1 gnu strd r6, [r8], #-32 +f24089e1| 1 gnu strd r4, [r9, r2] +f240a9e1| 1 gnu strd r4, [r9, r2]! +f24009e1| 1 gnu strd r4, [r9, -r2] +f24029e1| 1 gnu strd r4, [r9, -r2]! +0010b2e4| 1 gnu ldrt r1, [r2], #0 +2010b2e4| 1 gnu ldrt r1, [r2], #32 +201032e4| 1 gnu ldrt r1, [r2], #-32 +0040bde4| 1 gnu ldrt r4, [sp], #0 +2040bde4| 1 gnu ldrt r4, [sp], #32 +20403de4| 1 gnu ldrt r4, [sp], #-32 +2314b2e6| 1 gnu ldrt r1, [r2], r3, lsr #8 +0314b2e6| 1 gnu ldrt r1, [r2], r3, lsl #8 +4314b2e6| 1 gnu ldrt r1, [r2], r3, asr #8 +6314b2e6| 1 gnu ldrt r1, [r2], r3, ror #8 +231432e6| 1 gnu ldrt r1, [r2], -r3, lsr #8 +031432e6| 1 gnu ldrt r1, [r2], -r3, lsl #8 +431432e6| 1 gnu ldrt r1, [r2], -r3, asr #8 +631432e6| 1 gnu ldrt r1, [r2], -r3, ror #8 +0010a2e4| 1 gnu strt r1, [r2], #0 +2010a2e4| 1 gnu strt r1, [r2], #32 +201022e4| 1 gnu strt r1, [r2], #-32 +0040ade4| 1 gnu strt r4, [sp], #0 +2040ade4| 1 gnu strt r4, [sp], #32 +20402de4| 1 gnu strt r4, [sp], #-32 +2314a2e6| 1 gnu strt r1, [r2], r3, lsr #8 +0314a2e6| 1 gnu strt r1, [r2], r3, lsl #8 +4314a2e6| 1 gnu strt r1, [r2], r3, asr #8 +6314a2e6| 1 gnu strt r1, [r2], r3, ror #8 +231422e6| 1 gnu strt r1, [r2], -r3, lsr #8 +031422e6| 1 gnu strt r1, [r2], -r3, lsl #8 +431422e6| 1 gnu strt r1, [r2], -r3, asr #8 +631422e6| 1 gnu strt r1, [r2], -r3, ror #8 +0010f2e4| 1 gnu ldrbt r1, [r2], #0 +2010f2e4| 1 gnu ldrbt r1, [r2], #32 +201072e4| 1 gnu ldrbt r1, [r2], #-32 +0040fde4| 1 gnu ldrbt r4, [sp], #0 +2040fde4| 1 gnu ldrbt r4, [sp], #32 +20407de4| 1 gnu ldrbt r4, [sp], #-32 +2314f2e6| 1 gnu ldrbt r1, [r2], r3, lsr #8 +0314f2e6| 1 gnu ldrbt r1, [r2], r3, lsl #8 +4314f2e6| 1 gnu ldrbt r1, [r2], r3, asr #8 +6314f2e6| 1 gnu ldrbt r1, [r2], r3, ror #8 +231472e6| 1 gnu ldrbt r1, [r2], -r3, lsr #8 +031472e6| 1 gnu ldrbt r1, [r2], -r3, lsl #8 +431472e6| 1 gnu ldrbt r1, [r2], -r3, asr #8 +631472e6| 1 gnu ldrbt r1, [r2], -r3, ror #8 +0010e2e4| 1 gnu strbt r1, [r2], #0 +2010e2e4| 1 gnu strbt r1, [r2], #32 +201062e4| 1 gnu strbt r1, [r2], #-32 +0040ede4| 1 gnu strbt r4, [sp], #0 +2040ede4| 1 gnu strbt r4, [sp], #32 +20406de4| 1 gnu strbt r4, [sp], #-32 +2314e2e6| 1 gnu strbt r1, [r2], r3, lsr #8 +0314e2e6| 1 gnu strbt r1, [r2], r3, lsl #8 +4314e2e6| 1 gnu strbt r1, [r2], r3, asr #8 +6314e2e6| 1 gnu strbt r1, [r2], r3, ror #8 +231462e6| 1 gnu strbt r1, [r2], -r3, lsr #8 +031462e6| 1 gnu strbt r1, [r2], -r3, lsl #8 +431462e6| 1 gnu strbt r1, [r2], -r3, asr #8 +631462e6| 1 gnu strbt r1, [r2], -r3, ror #8 +d010f2e0| 1 gnu ldrsbt r1, [r2], #0 +d012f2e0| 1 gnu ldrsbt r1, [r2], #32 +d01272e0| 1 gnu ldrsbt r1, [r2], #-32 +d040fde0| 1 gnu ldrsbt r4, [sp], #0 +d042fde0| 1 gnu ldrsbt r4, [sp], #32 +d0427de0| 1 gnu ldrsbt r4, [sp], #-32 +d310b2e0| 1 gnu ldrsbt r1, [r2], r3 +d640bde0| 1 gnu ldrsbt r4, [sp], r6 +d31032e0| 1 gnu ldrsbt r1, [r2], -r3 +d6403de0| 1 gnu ldrsbt r4, [sp], -r6 +b010f2e0| 1 gnu ldrht r1, [r2], #0 +b012f2e0| 1 gnu ldrht r1, [r2], #32 +b01272e0| 1 gnu ldrht r1, [r2], #-32 +b040fde0| 1 gnu ldrht r4, [sp], #0 +b042fde0| 1 gnu ldrht r4, [sp], #32 +b0427de0| 1 gnu ldrht r4, [sp], #-32 +b310b2e0| 1 gnu ldrht r1, [r2], r3 +b640bde0| 1 gnu ldrht r4, [sp], r6 +b31032e0| 1 gnu ldrht r1, [r2], -r3 +b6403de0| 1 gnu ldrht r4, [sp], -r6 +f010f2e0| 1 gnu ldrsht r1, [r2], #0 +f012f2e0| 1 gnu ldrsht r1, [r2], #32 +f01272e0| 1 gnu ldrsht r1, [r2], #-32 +f040fde0| 1 gnu ldrsht r4, [sp], #0 +f042fde0| 1 gnu ldrsht r4, [sp], #32 +f0427de0| 1 gnu ldrsht r4, [sp], #-32 +f310b2e0| 1 gnu ldrsht r1, [r2], r3 +f640bde0| 1 gnu ldrsht r4, [sp], r6 +f31032e0| 1 gnu ldrsht r1, [r2], -r3 +f6403de0| 1 gnu ldrsht r4, [sp], -r6 +b010f2e0| 1 gnu ldrht r1, [r2], #0 +b012f2e0| 1 gnu ldrht r1, [r2], #32 +b01272e0| 1 gnu ldrht r1, [r2], #-32 +b040fde0| 1 gnu ldrht r4, [sp], #0 +b042fde0| 1 gnu ldrht r4, [sp], #32 +b0427de0| 1 gnu ldrht r4, [sp], #-32 +b310b2e0| 1 gnu ldrht r1, [r2], r3 +b640bde0| 1 gnu ldrht r4, [sp], r6 +b31032e0| 1 gnu ldrht r1, [r2], -r3 +b6403de0| 1 gnu ldrht r4, [sp], -r6 +b010e2e0| 1 gnu strht r1, [r2], #0 +b012e2e0| 1 gnu strht r1, [r2], #32 +b01262e0| 1 gnu strht r1, [r2], #-32 +b040ede0| 1 gnu strht r4, [sp], #0 +b042ede0| 1 gnu strht r4, [sp], #32 +b0426de0| 1 gnu strht r4, [sp], #-32 +b310a2e0| 1 gnu strht r1, [r2], r3 +b640ade0| 1 gnu strht r4, [sp], r6 +b31022e0| 1 gnu strht r1, [r2], -r3 +b6402de0| 1 gnu strht r4, [sp], -r6 +00f020e3| 1 gnu nop +445ab0ee| 1 gnu vmov.f32 s10, s8 +645af0ee| 1 gnu vmov.f32 s11, s9 +467bb0ee| 1 gnu vmov.f64 d7, d6 +104b08ee| 1 gnu vmov.32 d8[0], r4 +104b28ee| 1 gnu vmov.32 d8[1], r4 +108b14ee| 1 gnu vmov.32 r8, d4[0] +108b34ee| 1 gnu vmov.32 r8, d4[1] +c68abdee| 1 gnu vcvt.s32.f32 s16, s12 +e68afdee| 1 gnu vcvt.s32.f32 s17, s13 +c68abcee| 1 gnu vcvt.u32.f32 s16, s12 +e68afcee| 1 gnu vcvt.u32.f32 s17, s13 +c68bbdee| 1 gnu vcvt.s32.f64 s16, d6 +c68bfdee| 1 gnu vcvt.s32.f64 s17, d6 +c68bbcee| 1 gnu vcvt.u32.f64 s16, d6 +c68bfcee| 1 gnu vcvt.u32.f64 s17, d6 +c68ab8ee| 1 gnu vcvt.f32.s32 s16, s12 +e68af8ee| 1 gnu vcvt.f32.s32 s17, s13 +468ab8ee| 1 gnu vcvt.f32.u32 s16, s12 +668af8ee| 1 gnu vcvt.f32.u32 s17, s13 +c68bb8ee| 1 gnu vcvt.f64.s32 d8, s12 +e68bb8ee| 1 gnu vcvt.f64.s32 d8, s13 +468bb8ee| 1 gnu vcvt.f64.u32 d8, s12 +668bb8ee| 1 gnu vcvt.f64.u32 d8, s13 +c01ab7ee| 1 gnu vcvt.f64.f32 d1, s0 +e01ab7ee| 1 gnu vcvt.f64.f32 d1, s1 +c45bb7ee| 1 gnu vcvt.f32.f64 s10, d4 +c65bf7ee| 1 gnu vcvt.f32.f64 s11, d6 +102083e6| 1 gnu pkhbt r2, r3, r0 +102283e6| 1 gnu pkhbt r2, r3, r0, lsl #4 +502083e6| 1 gnu pkhtb r2, r3, r0, asr #32 +d02083e6| 1 gnu pkhtb r2, r3, r0, asr #1 +502283e6| 1 gnu pkhtb r2, r3, r0, asr #4 +faaf2de9| 1 gnu push {r1, r3, r4, r5, r6, r7, r8, r9, sl, fp, sp, pc} +04202de5| 1 gnu push {r2} +faafbde8| 1 gnu pop {r1, r3, r4, r5, r6, r7, r8, r9, sl, fp, sp, pc} +04209de4| 1 gnu pop {r2} +556003e1| 1 gnu qadd r6, r5, r3 +156f28e6| 1 gnu qadd16 r6, r8, r5 +956f28e6| 1 gnu qadd8 r6, r8, r5 +550044e1| 1 gnu qdadd r0, r5, r4 +550066e1| 1 gnu qdsub r0, r5, r6 +156f68e6| 1 gnu uqadd16 r6, r8, r5 +956f68e6| 1 gnu uqadd8 r6, r8, r5 +356f28e6| 1 gnu qasx r6, r8, r5 +556f28e6| 1 gnu qsax r6, r8, r5 +356f64e6| 1 gnu uqasx r6, r4, r5 +553f64e6| 1 gnu uqsax r3, r4, r5 +556022e1| 1 gnu qsub r6, r5, r2 +774f21e6| 1 gnu qsub16 r4, r1, r7 +f74f21e6| 1 gnu qsub8 r4, r1, r7 +774f61e6| 1 gnu uqsub16 r4, r1, r7 +f74f61e6| 1 gnu uqsub8 r4, r1, r7 +6670a0e1| 1 gnu rrx r7, r6 +6670b0e1| 1 gnu rrxs r7, r6 +112f13e6| 1 gnu sadd16 r2, r3, r1 +992f13e6| 1 gnu sadd8 r2, r3, r9 +112f33e6| 1 gnu shadd16 r2, r3, r1 +992f33e6| 1 gnu shadd8 r2, r3, r9 +712f13e6| 1 gnu ssub16 r2, r3, r1 +f92f13e6| 1 gnu ssub8 r2, r3, r9 +712f33e6| 1 gnu shsub16 r2, r3, r1 +f92f33e6| 1 gnu shsub8 r2, r3, r9 +112f53e6| 1 gnu uadd16 r2, r3, r1 +992f53e6| 1 gnu uadd8 r2, r3, r9 +112f73e6| 1 gnu uhadd16 r2, r3, r1 +992f73e6| 1 gnu uhadd8 r2, r3, r9 +712f53e6| 1 gnu usub16 r2, r3, r1 +f92f53e6| 1 gnu usub8 r2, r3, r9 +712f73e6| 1 gnu uhsub16 r2, r3, r1 +f92f73e6| 1 gnu uhsub8 r2, r3, r9 +332f14e6| 1 gnu sasx r2, r4, r3 +532f14e6| 1 gnu ssax r2, r4, r3 +332f54e6| 1 gnu uasx r2, r4, r3 +532f54e6| 1 gnu usax r2, r4, r3 +332f34e6| 1 gnu shasx r2, r4, r3 +532f34e6| 1 gnu shsax r2, r4, r3 +332f74e6| 1 gnu uhasx r2, r4, r3 +532f74e6| 1 gnu uhsax r2, r4, r3 +dc51afe7| 1 gnu sbfx r5, ip, #3, #16 +dc51efe7| 1 gnu ubfx r5, ip, #3, #16 +b12f88e6| 1 gnu sel r2, r8, r1 +000201f1| 1 gnu setend be +000001f1| 1 gnu setend le +04f020e3| 1 gnu sev +1155aae6| 1 gnu ssat r5, #11, r1, lsl #10 +5155aae6| 1 gnu ssat r5, #11, r1, asr #10 +335faae6| 1 gnu ssat16 r5, #11, r3 +1155eae6| 1 gnu usat r5, #10, r1, lsl #10 +5155eae6| 1 gnu usat r5, #10, r1, asr #10 +335feae6| 1 gnu usat16 r5, #10, r3 +7788a9e6| 1 gnu sxtab r8, r9, r7, ror #16 +778889e6| 1 gnu sxtab16 r8, r9, r7, ror #16 +7788b9e6| 1 gnu sxtah r8, r9, r7, ror #16 +7784afe6| 1 gnu sxtb r8, r7, ror #8 +778c8fe6| 1 gnu sxtb16 r8, r7, ror #24 +7780bfe6| 1 gnu sxth r8, r7 +7788e9e6| 1 gnu uxtab r8, r9, r7, ror #16 +7788c9e6| 1 gnu uxtab16 r8, r9, r7, ror #16 +7788f9e6| 1 gnu uxtah r8, r9, r7, ror #16 +7784efe6| 1 gnu uxtb r8, r7, ror #8 +778ccfe6| 1 gnu uxtb16 r8, r7, ror #24 +7780ffe6| 1 gnu uxth r8, r7 +11f288e7| 1 gnu usad8 r8, r1, r2 +112388e7| 1 gnu usada8 r8, r1, r3, r2 +02f020e3| 1 gnu wfe +03f020e3| 1 gnu wfi +01f020e3| 1 gnu yield diff --git a/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/arg.go b/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/arg.go new file mode 100644 index 0000000000..96df14dfaa --- /dev/null +++ b/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/arg.go @@ -0,0 +1,494 @@ +// Generated by ARM internal tool +// DO NOT EDIT + +// Copyright 2017 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package arm64asm + +// Naming for Go decoder arguments: +// +// - arg_Wd: a W register encoded in the Rd[4:0] field (31 is wzr) +// +// - arg_Xd: a X register encoded in the Rd[4:0] field (31 is xzr) +// +// - arg_Wds: a W register encoded in the Rd[4:0] field (31 is wsp) +// +// - arg_Xds: a X register encoded in the Rd[4:0] field (31 is sp) +// +// - arg_Wn: encoded in Rn[9:5] +// +// - arg_Wm: encoded in Rm[20:16] +// +// - arg_Wm_extend__UXTB_0__UXTH_1__LSL_UXTW_2__UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4: +// a W register encoded in Rm with an extend encoded in option[15:13] and an amount +// encoded in imm3[12:10] in the range [0,4]. +// +// - arg_Rm_extend__UXTB_0__UXTH_1__UXTW_2__LSL_UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4: +// a W or X register encoded in Rm with an extend encoded in option[15:13] and an +// amount encoded in imm3[12:10] in the range [0,4]. If the extend is UXTX or SXTX, +// it's an X register else, it's a W register. +// +// - arg_Wm_shift__LSL_0__LSR_1__ASR_2__0_31: +// a W register encoded in Rm with a shift encoded in shift[23:22] and an amount +// encoded in imm6[15:10] in the range [0,31]. +// +// - arg_IAddSub: +// An immediate for a add/sub instruction encoded in imm12[21:10] with an optional +// left shift of 12 encoded in shift[23:22]. +// +// - arg_Rt_31_1__W_0__X_1: +// a W or X register encoded in Rt[4:0]. The width specifier is encoded in the field +// [31:31] (offset 31, bit count 1) and the register is W for 0 and X for 1. +// +// - arg_[s|u]label_FIELDS_POWER: +// a program label encoded as "FIELDS" times 2^POWER in the range [MIN, MAX] (determined +// by signd/unsigned, FIELDS and POWER), e.g. +// arg_slabel_imm14_2 +// arg_slabel_imm19_2 +// arg_slabel_imm26_2 +// arg_slabel_immhi_immlo_0 +// arg_slabel_immhi_immlo_12 +// +// - arg_Xns_mem_post_imm7_8_signed: +// addressing mode of post-index with a base register: Xns and a signed offset encoded +// in the "imm7" field times 8 +// +// - arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__3_1: +// addressing mode of extended register with a base register: Xns, an offset register +// (|) with an extend encoded in option[15:13] and a shift amount encoded in +// S[12:12] in the range [0,3] (S=0:0, S=1:3). +// +// - arg_Xns_mem_optional_imm12_4_unsigned: +// addressing mode of unsigned offset with a base register: Xns and an optional unsigned +// offset encoded in the "imm12" field times 4 +// +// - arg_Xns_mem_wb_imm7_4_signed: +// addressing mode of pre-index with a base register: Xns and the signed offset encoded +// in the "imm7" field times 4 +// +// - arg_Xns_mem_post_size_1_8_unsigned__4_0__8_1__16_2__32_3: +// a post-index immediate offset, encoded in the "size" field. It can have the following values: +// #4 when size = 00 +// #8 when size = 01 +// #16 when size = 10 +// #32 when size = 11 +// +// - arg_immediate_0_127_CRm_op2: +// an immediate encoded in "CRm:op2" in the range 0 to 127 +// +// - arg_immediate_bitmask_64_N_imms_immr: +// a bitmask immediate for 64-bit variant and encoded in "N:imms:immr" +// +// - arg_immediate_SBFX_SBFM_64M_bitfield_width_64_imms: +// an immediate for the bitfield of SBFX 64-bit variant +// +// - arg_immediate_shift_32_implicit_inverse_imm16_hw: +// a 32-bit immediate of the bitwise inverse of which can be encoded in "imm16:hw" +// +// - arg_cond_[Not]AllowALNV_[Invert|Normal]: +// a standard condition, encoded in the "cond" field, excluding (NotAllow) AL and NV with +// its least significant bit [Yes|No] inverted, e.g. +// arg_cond_AllowALNV_Normal +// arg_cond_NotAllowALNV_Invert +// +// - arg_immediate_OptLSL_amount_16_0_48: +// An immediate for MOV[KNZ] instruction encoded in imm16[20:5] with an optional +// left shift of 16 in the range [0, 48] encoded in hw[22, 21] +// +// - arg_immediate_0_width_m1_immh_immb__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4__UIntimmhimmb64_8: +// the left shift amount, in the range 0 to the operand width in bits minus 1, +// encoded in the "immh:immb" field. It can have the following values: +// (UInt(immh:immb)-8) when immh = 0001 +// (UInt(immh:immb)-16) when immh = 001x +// (UInt(immh:immb)-32) when immh = 01xx +// (UInt(immh:immb)-64) when immh = 1xxx +// +// - arg_immediate_1_width_immh_immb__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4: +// the right shift amount, in the range 1 to the destination operand width in +// bits, encoded in the "immh:immb" field. It can have the following values: +// (16-UInt(immh:immb)) when immh = 0001 +// (32-UInt(immh:immb)) when immh = 001x +// (64-UInt(immh:immb)) when immh = 01xx +// +// - arg_immediate_8x8_a_b_c_d_e_f_g_h: +// a 64-bit immediate 'aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh', +// encoded in "a:b:c:d:e:f:g:h". +// +// - arg_immediate_fbits_min_1_max_32_sub_64_scale: +// the number of bits after the binary point in the fixed-point destination, +// in the range 1 to 32, encoded as 64 minus "scale". +// +// - arg_immediate_floatzero: #0.0 +// +// - arg_immediate_exp_3_pre_4_a_b_c_d_e_f_g_h: +// a signed floating-point constant with 3-bit exponent and normalized 4 bits of precision, +// encoded in "a:b:c:d:e:f:g:h" +// +// - arg_immediate_fbits_min_1_max_0_sub_0_immh_immb__64UIntimmhimmb_4__128UIntimmhimmb_8: +// the number of fractional bits, in the range 1 to the operand width, encoded +// in the "immh:immb" field. It can have the following values: +// (64-UInt(immh:immb)) when immh = 01xx +// (128-UInt(immh:immb)) when immh = 1xxx +// +// - arg_immediate_index_Q_imm4__imm4lt20gt_00__imm4_10: +// the lowest numbered byte element to be extracted, encoded in the "Q:imm4" field. +// It can have the following values: +// imm4<2:0> when Q = 0, imm4<3> = 0 +// imm4 when Q = 1, imm4<3> = x +// +// - arg_sysop_AT_SYS_CR_system: +// system operation for system instruction: AT encoded in the "op1:CRm<0>:op2" field +// +// - arg_prfop_Rt: +// prefectch operation encoded in the "Rt" +// +// - arg_sysreg_o0_op1_CRn_CRm_op2: +// system register name encoded in the "o0:op1:CRn:CRm:op2" +// +// - arg_pstatefield_op1_op2__SPSel_05__DAIFSet_36__DAIFClr_37: +// PSTATE field name encoded in the "op1:op2" field +// +// - arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31: +// one register with arrangement specifier encoded in the "size:Q" field which can have the following values: +// 8B when size = 00, Q = 0 +// 16B when size = 00, Q = 1 +// 4H when size = 01, Q = 0 +// 8H when size = 01, Q = 1 +// 2S when size = 10, Q = 0 +// 4S when size = 10, Q = 1 +// 2D when size = 11, Q = 1 +// The encoding size = 11, Q = 0 is reserved. +// +// - arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31: +// three registers with arrangement specifier encoded in the "size:Q" field which can have the following values: +// 8B when size = 00, Q = 0 +// 16B when size = 00, Q = 1 +// 4H when size = 01, Q = 0 +// 8H when size = 01, Q = 1 +// 2S when size = 10, Q = 0 +// 4S when size = 10, Q = 1 +// 2D when size = 11, Q = 1 +// The encoding size = 11, Q = 0 is reserved. +// +// - arg_Vt_1_arrangement_H_index__Q_S_size_1: +// one register with arrangement:H and element index encoded in "Q:S:size<1>". + +type instArg uint16 + +const ( + _ instArg = iota + arg_Bt + arg_Cm + arg_Cn + arg_cond_AllowALNV_Normal + arg_conditional + arg_cond_NotAllowALNV_Invert + arg_Da + arg_Dd + arg_Dm + arg_Dn + arg_Dt + arg_Dt2 + arg_Hd + arg_Hn + arg_Ht + arg_IAddSub + arg_immediate_0_127_CRm_op2 + arg_immediate_0_15_CRm + arg_immediate_0_15_nzcv + arg_immediate_0_31_imm5 + arg_immediate_0_31_immr + arg_immediate_0_31_imms + arg_immediate_0_63_b5_b40 + arg_immediate_0_63_immh_immb__UIntimmhimmb64_8 + arg_immediate_0_63_immr + arg_immediate_0_63_imms + arg_immediate_0_65535_imm16 + arg_immediate_0_7_op1 + arg_immediate_0_7_op2 + arg_immediate_0_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4 + arg_immediate_0_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4__UIntimmhimmb64_8 + arg_immediate_0_width_m1_immh_immb__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4__UIntimmhimmb64_8 + arg_immediate_0_width_size__8_0__16_1__32_2 + arg_immediate_1_64_immh_immb__128UIntimmhimmb_8 + arg_immediate_1_width_immh_immb__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4 + arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4 + arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4__128UIntimmhimmb_8 + arg_immediate_8x8_a_b_c_d_e_f_g_h + arg_immediate_ASR_SBFM_32M_bitfield_0_31_immr + arg_immediate_ASR_SBFM_64M_bitfield_0_63_immr + arg_immediate_BFI_BFM_32M_bitfield_lsb_32_immr + arg_immediate_BFI_BFM_32M_bitfield_width_32_imms + arg_immediate_BFI_BFM_64M_bitfield_lsb_64_immr + arg_immediate_BFI_BFM_64M_bitfield_width_64_imms + arg_immediate_BFXIL_BFM_32M_bitfield_lsb_32_immr + arg_immediate_BFXIL_BFM_32M_bitfield_width_32_imms + arg_immediate_BFXIL_BFM_64M_bitfield_lsb_64_immr + arg_immediate_BFXIL_BFM_64M_bitfield_width_64_imms + arg_immediate_bitmask_32_imms_immr + arg_immediate_bitmask_64_N_imms_immr + arg_immediate_exp_3_pre_4_a_b_c_d_e_f_g_h + arg_immediate_exp_3_pre_4_imm8 + arg_immediate_fbits_min_1_max_0_sub_0_immh_immb__64UIntimmhimmb_4__128UIntimmhimmb_8 + arg_immediate_fbits_min_1_max_0_sub_0_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__64UIntimmhimmb_4__128UIntimmhimmb_8 + arg_immediate_fbits_min_1_max_32_sub_64_scale + arg_immediate_fbits_min_1_max_64_sub_64_scale + arg_immediate_floatzero + arg_immediate_index_Q_imm4__imm4lt20gt_00__imm4_10 + arg_immediate_LSL_UBFM_32M_bitfield_0_31_immr + arg_immediate_LSL_UBFM_64M_bitfield_0_63_immr + arg_immediate_LSR_UBFM_32M_bitfield_0_31_immr + arg_immediate_LSR_UBFM_64M_bitfield_0_63_immr + arg_immediate_MSL__a_b_c_d_e_f_g_h_cmode__8_0__16_1 + arg_immediate_optional_0_15_CRm + arg_immediate_optional_0_65535_imm16 + arg_immediate_OptLSL__a_b_c_d_e_f_g_h_cmode__0_0__8_1 + arg_immediate_OptLSL__a_b_c_d_e_f_g_h_cmode__0_0__8_1__16_2__24_3 + arg_immediate_OptLSL_amount_16_0_16 + arg_immediate_OptLSL_amount_16_0_48 + arg_immediate_OptLSLZero__a_b_c_d_e_f_g_h + arg_immediate_SBFIZ_SBFM_32M_bitfield_lsb_32_immr + arg_immediate_SBFIZ_SBFM_32M_bitfield_width_32_imms + arg_immediate_SBFIZ_SBFM_64M_bitfield_lsb_64_immr + arg_immediate_SBFIZ_SBFM_64M_bitfield_width_64_imms + arg_immediate_SBFX_SBFM_32M_bitfield_lsb_32_immr + arg_immediate_SBFX_SBFM_32M_bitfield_width_32_imms + arg_immediate_SBFX_SBFM_64M_bitfield_lsb_64_immr + arg_immediate_SBFX_SBFM_64M_bitfield_width_64_imms + arg_immediate_shift_32_implicit_imm16_hw + arg_immediate_shift_32_implicit_inverse_imm16_hw + arg_immediate_shift_64_implicit_imm16_hw + arg_immediate_shift_64_implicit_inverse_imm16_hw + arg_immediate_UBFIZ_UBFM_32M_bitfield_lsb_32_immr + arg_immediate_UBFIZ_UBFM_32M_bitfield_width_32_imms + arg_immediate_UBFIZ_UBFM_64M_bitfield_lsb_64_immr + arg_immediate_UBFIZ_UBFM_64M_bitfield_width_64_imms + arg_immediate_UBFX_UBFM_32M_bitfield_lsb_32_immr + arg_immediate_UBFX_UBFM_32M_bitfield_width_32_imms + arg_immediate_UBFX_UBFM_64M_bitfield_lsb_64_immr + arg_immediate_UBFX_UBFM_64M_bitfield_width_64_imms + arg_immediate_zero + arg_option_DMB_BO_system_CRm + arg_option_DSB_BO_system_CRm + arg_option_ISB_BI_system_CRm + arg_prfop_Rt + arg_pstatefield_op1_op2__SPSel_05__DAIFSet_36__DAIFClr_37 + arg_Qd + arg_Qn + arg_Qt + arg_Qt2 + arg_Rm_extend__UXTB_0__UXTH_1__UXTW_2__LSL_UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4 + arg_Rn_16_5__W_1__W_2__W_4__X_8 + arg_Rt_31_1__W_0__X_1 + arg_Sa + arg_Sd + arg_slabel_imm14_2 + arg_slabel_imm19_2 + arg_slabel_imm26_2 + arg_slabel_immhi_immlo_0 + arg_slabel_immhi_immlo_12 + arg_Sm + arg_Sn + arg_St + arg_St2 + arg_sysop_AT_SYS_CR_system + arg_sysop_DC_SYS_CR_system + arg_sysop_IC_SYS_CR_system + arg_sysop_SYS_CR_system + arg_sysop_TLBI_SYS_CR_system + arg_sysreg_o0_op1_CRn_CRm_op2 + arg_Vd_16_5__B_1__H_2__S_4__D_8 + arg_Vd_19_4__B_1__H_2__S_4 + arg_Vd_19_4__B_1__H_2__S_4__D_8 + arg_Vd_19_4__D_8 + arg_Vd_19_4__S_4__D_8 + arg_Vd_22_1__S_0 + arg_Vd_22_1__S_0__D_1 + arg_Vd_22_1__S_1 + arg_Vd_22_2__B_0__H_1__S_2 + arg_Vd_22_2__B_0__H_1__S_2__D_3 + arg_Vd_22_2__D_3 + arg_Vd_22_2__H_0__S_1__D_2 + arg_Vd_22_2__H_1__S_2 + arg_Vd_22_2__S_1__D_2 + arg_Vd_arrangement_16B + arg_Vd_arrangement_2D + arg_Vd_arrangement_4S + arg_Vd_arrangement_D_index__1 + arg_Vd_arrangement_imm5___B_1__H_2__S_4__D_8_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4__imm5lt4gt_8_1 + arg_Vd_arrangement_imm5_Q___8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81 + arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__2S_40__4S_41__2D_81 + arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41 + arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81 + arg_Vd_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4 + arg_Vd_arrangement_Q___2S_0__4S_1 + arg_Vd_arrangement_Q___4H_0__8H_1 + arg_Vd_arrangement_Q___8B_0__16B_1 + arg_Vd_arrangement_Q_sz___2S_00__4S_10__2D_11 + arg_Vd_arrangement_size___4S_1__2D_2 + arg_Vd_arrangement_size___8H_0__1Q_3 + arg_Vd_arrangement_size___8H_0__4S_1__2D_2 + arg_Vd_arrangement_size_Q___4H_00__8H_01__2S_10__4S_11__1D_20__2D_21 + arg_Vd_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21 + arg_Vd_arrangement_size_Q___8B_00__16B_01 + arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11 + arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21 + arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31 + arg_Vd_arrangement_sz___4S_0__2D_1 + arg_Vd_arrangement_sz_Q___2S_00__4S_01 + arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11 + arg_Vd_arrangement_sz_Q___2S_10__4S_11 + arg_Vd_arrangement_sz_Q___4H_00__8H_01__2S_10__4S_11 + arg_Vm_22_1__S_0__D_1 + arg_Vm_22_2__B_0__H_1__S_2__D_3 + arg_Vm_22_2__D_3 + arg_Vm_22_2__H_1__S_2 + arg_Vm_arrangement_4S + arg_Vm_arrangement_Q___8B_0__16B_1 + arg_Vm_arrangement_size___8H_0__4S_1__2D_2 + arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1 + arg_Vm_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21 + arg_Vm_arrangement_size_Q___8B_00__16B_01 + arg_Vm_arrangement_size_Q___8B_00__16B_01__1D_30__2D_31 + arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21 + arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31 + arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11 + arg_Vm_arrangement_sz___S_0__D_1_index__sz_L_H__HL_00__H_10_1 + arg_Vn_19_4__B_1__H_2__S_4__D_8 + arg_Vn_19_4__D_8 + arg_Vn_19_4__H_1__S_2__D_4 + arg_Vn_19_4__S_4__D_8 + arg_Vn_1_arrangement_16B + arg_Vn_22_1__D_1 + arg_Vn_22_1__S_0__D_1 + arg_Vn_22_2__B_0__H_1__S_2__D_3 + arg_Vn_22_2__D_3 + arg_Vn_22_2__H_0__S_1__D_2 + arg_Vn_22_2__H_1__S_2 + arg_Vn_2_arrangement_16B + arg_Vn_3_arrangement_16B + arg_Vn_4_arrangement_16B + arg_Vn_arrangement_16B + arg_Vn_arrangement_4S + arg_Vn_arrangement_D_index__1 + arg_Vn_arrangement_D_index__imm5_1 + arg_Vn_arrangement_imm5___B_1__H_2_index__imm5__imm5lt41gt_1__imm5lt42gt_2_1 + arg_Vn_arrangement_imm5___B_1__H_2__S_4__D_8_index__imm5_imm4__imm4lt30gt_1__imm4lt31gt_2__imm4lt32gt_4__imm4lt3gt_8_1 + arg_Vn_arrangement_imm5___B_1__H_2__S_4__D_8_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4__imm5lt4gt_8_1 + arg_Vn_arrangement_imm5___B_1__H_2__S_4_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4_1 + arg_Vn_arrangement_imm5___D_8_index__imm5_1 + arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__2S_40__4S_41__2D_81 + arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41 + arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81 + arg_Vn_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4 + arg_Vn_arrangement_Q___8B_0__16B_1 + arg_Vn_arrangement_Q_sz___2S_00__4S_10__2D_11 + arg_Vn_arrangement_Q_sz___4S_10 + arg_Vn_arrangement_S_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4_1 + arg_Vn_arrangement_size___2D_3 + arg_Vn_arrangement_size___8H_0__4S_1__2D_2 + arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21 + arg_Vn_arrangement_size_Q___8B_00__16B_01 + arg_Vn_arrangement_size_Q___8B_00__16B_01__1D_30__2D_31 + arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11 + arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21 + arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31 + arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__4S_21 + arg_Vn_arrangement_sz___2D_1 + arg_Vn_arrangement_sz___2S_0__2D_1 + arg_Vn_arrangement_sz___4S_0__2D_1 + arg_Vn_arrangement_sz_Q___2S_00__4S_01 + arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11 + arg_Vn_arrangement_sz_Q___4H_00__8H_01__2S_10__4S_11 + arg_Vt_1_arrangement_B_index__Q_S_size_1 + arg_Vt_1_arrangement_D_index__Q_1 + arg_Vt_1_arrangement_H_index__Q_S_size_1 + arg_Vt_1_arrangement_S_index__Q_S_1 + arg_Vt_1_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31 + arg_Vt_2_arrangement_B_index__Q_S_size_1 + arg_Vt_2_arrangement_D_index__Q_1 + arg_Vt_2_arrangement_H_index__Q_S_size_1 + arg_Vt_2_arrangement_S_index__Q_S_1 + arg_Vt_2_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31 + arg_Vt_2_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31 + arg_Vt_3_arrangement_B_index__Q_S_size_1 + arg_Vt_3_arrangement_D_index__Q_1 + arg_Vt_3_arrangement_H_index__Q_S_size_1 + arg_Vt_3_arrangement_S_index__Q_S_1 + arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31 + arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31 + arg_Vt_4_arrangement_B_index__Q_S_size_1 + arg_Vt_4_arrangement_D_index__Q_1 + arg_Vt_4_arrangement_H_index__Q_S_size_1 + arg_Vt_4_arrangement_S_index__Q_S_1 + arg_Vt_4_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31 + arg_Vt_4_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31 + arg_Wa + arg_Wd + arg_Wds + arg_Wm + arg_Wm_extend__UXTB_0__UXTH_1__LSL_UXTW_2__UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4 + arg_Wm_shift__LSL_0__LSR_1__ASR_2__0_31 + arg_Wm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_31 + arg_Wn + arg_Wns + arg_Ws + arg_Wt + arg_Wt2 + arg_Xa + arg_Xd + arg_Xds + arg_Xm + arg_Xm_shift__LSL_0__LSR_1__ASR_2__0_63 + arg_Xm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_63 + arg_Xn + arg_Xns + arg_Xns_mem + arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__1_1 + arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__2_1 + arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__3_1 + arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__4_1 + arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__absent_0__0_1 + arg_Xns_mem_offset + arg_Xns_mem_optional_imm12_16_unsigned + arg_Xns_mem_optional_imm12_1_unsigned + arg_Xns_mem_optional_imm12_2_unsigned + arg_Xns_mem_optional_imm12_4_unsigned + arg_Xns_mem_optional_imm12_8_unsigned + arg_Xns_mem_optional_imm7_16_signed + arg_Xns_mem_optional_imm7_4_signed + arg_Xns_mem_optional_imm7_8_signed + arg_Xns_mem_optional_imm9_1_signed + arg_Xns_mem_post_fixedimm_1 + arg_Xns_mem_post_fixedimm_12 + arg_Xns_mem_post_fixedimm_16 + arg_Xns_mem_post_fixedimm_2 + arg_Xns_mem_post_fixedimm_24 + arg_Xns_mem_post_fixedimm_3 + arg_Xns_mem_post_fixedimm_32 + arg_Xns_mem_post_fixedimm_4 + arg_Xns_mem_post_fixedimm_6 + arg_Xns_mem_post_fixedimm_8 + arg_Xns_mem_post_imm7_16_signed + arg_Xns_mem_post_imm7_4_signed + arg_Xns_mem_post_imm7_8_signed + arg_Xns_mem_post_imm9_1_signed + arg_Xns_mem_post_Q__16_0__32_1 + arg_Xns_mem_post_Q__24_0__48_1 + arg_Xns_mem_post_Q__32_0__64_1 + arg_Xns_mem_post_Q__8_0__16_1 + arg_Xns_mem_post_size__1_0__2_1__4_2__8_3 + arg_Xns_mem_post_size__2_0__4_1__8_2__16_3 + arg_Xns_mem_post_size__3_0__6_1__12_2__24_3 + arg_Xns_mem_post_size__4_0__8_1__16_2__32_3 + arg_Xns_mem_post_Xm + arg_Xns_mem_wb_imm7_16_signed + arg_Xns_mem_wb_imm7_4_signed + arg_Xns_mem_wb_imm7_8_signed + arg_Xns_mem_wb_imm9_1_signed + arg_Xs + arg_Xt + arg_Xt2 +) diff --git a/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/condition.go b/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/condition.go new file mode 100755 index 0000000000..d673857212 --- /dev/null +++ b/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/condition.go @@ -0,0 +1,329 @@ +// Generated by ARM internal tool +// DO NOT EDIT + +// Copyright 2017 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package arm64asm + +// Following functions are used as the predicator: canDecode of according instruction +// Refer to instFormat inside decode.go for more details + +func at_sys_cr_system_cond(instr uint32) bool { + return sys_op_4((instr>>16)&0x7, 0x7, 0x8, (instr>>5)&0x7) == Sys_AT +} + +func bfi_bfm_32m_bitfield_cond(instr uint32) bool { + return (instr>>5)&0x1f != 0x1f && uint8((instr>>10)&0x3f) < uint8((instr>>16)&0x3f) +} + +func bfi_bfm_64m_bitfield_cond(instr uint32) bool { + return (instr>>5)&0x1f != 0x1f && uint8((instr>>10)&0x3f) < uint8((instr>>16)&0x3f) +} + +func bfxil_bfm_32m_bitfield_cond(instr uint32) bool { + return uint8((instr>>10)&0x3f) >= uint8((instr>>16)&0x3f) +} + +func bfxil_bfm_64m_bitfield_cond(instr uint32) bool { + return uint8((instr>>10)&0x3f) >= uint8((instr>>16)&0x3f) +} + +func cinc_csinc_32_condsel_cond(instr uint32) bool { + return instr&0x1f0000 != 0x1f0000 && instr&0xe000 != 0xe000 && instr&0x3e0 != 0x3e0 && (instr>>5)&0x1f == (instr>>16)&0x1f +} + +func cinc_csinc_64_condsel_cond(instr uint32) bool { + return instr&0x1f0000 != 0x1f0000 && instr&0xe000 != 0xe000 && instr&0x3e0 != 0x3e0 && (instr>>5)&0x1f == (instr>>16)&0x1f +} + +func cinv_csinv_32_condsel_cond(instr uint32) bool { + return instr&0x1f0000 != 0x1f0000 && instr&0xe000 != 0xe000 && instr&0x3e0 != 0x3e0 && (instr>>5)&0x1f == (instr>>16)&0x1f +} + +func cinv_csinv_64_condsel_cond(instr uint32) bool { + return instr&0x1f0000 != 0x1f0000 && instr&0xe000 != 0xe000 && instr&0x3e0 != 0x3e0 && (instr>>5)&0x1f == (instr>>16)&0x1f +} + +func cneg_csneg_32_condsel_cond(instr uint32) bool { + return instr&0xe000 != 0xe000 && (instr>>5)&0x1f == (instr>>16)&0x1f +} + +func cneg_csneg_64_condsel_cond(instr uint32) bool { + return instr&0xe000 != 0xe000 && (instr>>5)&0x1f == (instr>>16)&0x1f +} + +func csinc_general_cond(instr uint32) bool { + return instr&0xe000 != 0xe000 +} +func csinv_general_cond(instr uint32) bool { + return instr&0xe000 != 0xe000 +} +func dc_sys_cr_system_cond(instr uint32) bool { + return sys_op_4((instr>>16)&0x7, 0x7, (instr>>8)&0xf, (instr>>5)&0x7) == Sys_DC +} + +func ic_sys_cr_system_cond(instr uint32) bool { + return sys_op_4((instr>>16)&0x7, 0x7, (instr>>8)&0xf, (instr>>5)&0x7) == Sys_IC +} + +func lsl_ubfm_32m_bitfield_cond(instr uint32) bool { + return instr&0xfc00 != 0x7c00 && (instr>>10)&0x3f+1 == (instr>>16)&0x3f +} + +func lsl_ubfm_64m_bitfield_cond(instr uint32) bool { + return instr&0xfc00 != 0xfc00 && (instr>>10)&0x3f+1 == (instr>>16)&0x3f +} + +func mov_orr_32_log_imm_cond(instr uint32) bool { + return !move_wide_preferred_4((instr>>31)&0x1, (instr>>22)&0x1, (instr>>10)&0x3f, (instr>>16)&0x3f) +} + +func mov_orr_64_log_imm_cond(instr uint32) bool { + return !move_wide_preferred_4((instr>>31)&0x1, (instr>>22)&0x1, (instr>>10)&0x3f, (instr>>16)&0x3f) +} + +func mov_movn_32_movewide_cond(instr uint32) bool { + return !(is_zero((instr>>5)&0xffff) && (instr>>21)&0x3 != 0x0) && !is_ones_n16((instr>>5)&0xffff) +} + +func mov_movn_64_movewide_cond(instr uint32) bool { + return !(is_zero((instr>>5)&0xffff) && (instr>>21)&0x3 != 0x0) +} + +func mov_add_32_addsub_imm_cond(instr uint32) bool { + return instr&0x1f == 0x1f || (instr>>5)&0x1f == 0x1f +} + +func mov_add_64_addsub_imm_cond(instr uint32) bool { + return instr&0x1f == 0x1f || (instr>>5)&0x1f == 0x1f +} + +func mov_movz_32_movewide_cond(instr uint32) bool { + return !(is_zero((instr>>5)&0xffff) && (instr>>21)&0x3 != 0x0) +} + +func mov_movz_64_movewide_cond(instr uint32) bool { + return !(is_zero((instr>>5)&0xffff) && (instr>>21)&0x3 != 0x0) +} + +func ror_extr_32_extract_cond(instr uint32) bool { + return (instr>>5)&0x1f == (instr>>16)&0x1f +} + +func ror_extr_64_extract_cond(instr uint32) bool { + return (instr>>5)&0x1f == (instr>>16)&0x1f +} + +func sbfiz_sbfm_32m_bitfield_cond(instr uint32) bool { + return uint8((instr>>10)&0x3f) < uint8((instr>>16)&0x3f) +} + +func sbfiz_sbfm_64m_bitfield_cond(instr uint32) bool { + return uint8((instr>>10)&0x3f) < uint8((instr>>16)&0x3f) +} + +func sbfx_sbfm_32m_bitfield_cond(instr uint32) bool { + return bfxpreferred_4((instr>>31)&0x1, extract_bit((instr>>29)&0x3, 1), (instr>>10)&0x3f, (instr>>16)&0x3f) +} + +func sbfx_sbfm_64m_bitfield_cond(instr uint32) bool { + return bfxpreferred_4((instr>>31)&0x1, extract_bit((instr>>29)&0x3, 1), (instr>>10)&0x3f, (instr>>16)&0x3f) +} + +func tlbi_sys_cr_system_cond(instr uint32) bool { + return sys_op_4((instr>>16)&0x7, 0x8, (instr>>8)&0xf, (instr>>5)&0x7) == Sys_TLBI +} + +func ubfiz_ubfm_32m_bitfield_cond(instr uint32) bool { + return uint8((instr>>10)&0x3f) < uint8((instr>>16)&0x3f) +} + +func ubfiz_ubfm_64m_bitfield_cond(instr uint32) bool { + return uint8((instr>>10)&0x3f) < uint8((instr>>16)&0x3f) +} + +func ubfx_ubfm_32m_bitfield_cond(instr uint32) bool { + return bfxpreferred_4((instr>>31)&0x1, extract_bit((instr>>29)&0x3, 1), (instr>>10)&0x3f, (instr>>16)&0x3f) +} + +func ubfx_ubfm_64m_bitfield_cond(instr uint32) bool { + return bfxpreferred_4((instr>>31)&0x1, extract_bit((instr>>29)&0x3, 1), (instr>>10)&0x3f, (instr>>16)&0x3f) +} + +func fcvtzs_asisdshf_c_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func fcvtzs_asimdshf_c_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func fcvtzu_asisdshf_c_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func fcvtzu_asimdshf_c_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func mov_umov_asimdins_w_w_cond(instr uint32) bool { + return ((instr>>16)&0x1f)&0x7 == 0x4 +} + +func mov_umov_asimdins_x_x_cond(instr uint32) bool { + return ((instr>>16)&0x1f)&0xf == 0x8 +} + +func mov_orr_asimdsame_only_cond(instr uint32) bool { + return (instr>>16)&0x1f == (instr>>5)&0x1f +} + +func rshrn_asimdshf_n_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func scvtf_asisdshf_c_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func scvtf_asimdshf_c_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func shl_asisdshf_r_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func shl_asimdshf_r_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func shrn_asimdshf_n_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func sli_asisdshf_r_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func sli_asimdshf_r_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func sqrshrn_asisdshf_n_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func sqrshrn_asimdshf_n_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func sqrshrun_asisdshf_n_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func sqrshrun_asimdshf_n_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func sqshl_asisdshf_r_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func sqshl_asimdshf_r_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func sqshlu_asisdshf_r_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func sqshlu_asimdshf_r_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func sqshrn_asisdshf_n_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func sqshrn_asimdshf_n_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func sqshrun_asisdshf_n_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func sqshrun_asimdshf_n_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func sri_asisdshf_r_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func sri_asimdshf_r_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func srshr_asisdshf_r_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func srshr_asimdshf_r_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func srsra_asisdshf_r_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func srsra_asimdshf_r_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func sshll_asimdshf_l_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func sshr_asisdshf_r_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func sshr_asimdshf_r_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func ssra_asisdshf_r_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func ssra_asimdshf_r_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func sxtl_sshll_asimdshf_l_cond(instr uint32) bool { + return instr&0x780000 != 0x0 && bit_count((instr>>19)&0xf) == 1 +} + +func ucvtf_asisdshf_c_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func ucvtf_asimdshf_c_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func uqrshrn_asisdshf_n_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func uqrshrn_asimdshf_n_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func uqshl_asisdshf_r_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func uqshl_asimdshf_r_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func uqshrn_asisdshf_n_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func uqshrn_asimdshf_n_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func urshr_asisdshf_r_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func urshr_asimdshf_r_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func ursra_asisdshf_r_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func ursra_asimdshf_r_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func ushll_asimdshf_l_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func ushr_asisdshf_r_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func ushr_asimdshf_r_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func usra_asisdshf_r_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func usra_asimdshf_r_cond(instr uint32) bool { + return instr&0x780000 != 0x0 +} +func uxtl_ushll_asimdshf_l_cond(instr uint32) bool { + return instr&0x780000 != 0x0 && bit_count((instr>>19)&0xf) == 1 +} diff --git a/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/condition_util.go b/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/condition_util.go new file mode 100755 index 0000000000..62c0c3b0ac --- /dev/null +++ b/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/condition_util.go @@ -0,0 +1,81 @@ +// Copyright 2017 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package arm64asm + +func extract_bit(value, bit uint32) uint32 { + return (value >> bit) & 1 +} + +func bfxpreferred_4(sf, opc1, imms, immr uint32) bool { + if imms < immr { + return false + } + if (imms>>5 == sf) && (imms&0x1f == 0x1f) { + return false + } + if immr == 0 { + if sf == 0 && (imms == 7 || imms == 15) { + return false + } + if sf == 1 && opc1 == 0 && (imms == 7 || + imms == 15 || imms == 31) { + return false + } + } + return true +} + +func move_wide_preferred_4(sf, N, imms, immr uint32) bool { + if sf == 1 && N != 1 { + return false + } + if sf == 0 && !(N == 0 && ((imms>>5)&1) == 0) { + return false + } + if imms < 16 { + return (-immr)%16 <= (15 - imms) + } + width := uint32(32) + if sf == 1 { + width = uint32(64) + } + if imms >= (width - 15) { + return (immr % 16) <= (imms - (width - 15)) + } + return false +} + +type Sys uint8 + +const ( + Sys_AT Sys = iota + Sys_DC + Sys_IC + Sys_TLBI + Sys_SYS +) + +func sys_op_4(op1, crn, crm, op2 uint32) Sys { + // TODO: system instruction + return Sys_SYS +} + +func is_zero(x uint32) bool { + return x == 0 +} + +func is_ones_n16(x uint32) bool { + return x == 0xffff +} + +func bit_count(x uint32) uint8 { + var count uint8 + for count = 0; x > 0; x >>= 1 { + if (x & 1) == 1 { + count++ + } + } + return count +} diff --git a/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/decode.go b/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/decode.go new file mode 100644 index 0000000000..5e29c47696 --- /dev/null +++ b/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/decode.go @@ -0,0 +1,2768 @@ +// Copyright 2017 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package arm64asm + +import ( + "encoding/binary" + "fmt" +) + +type instArgs [5]instArg + +// An instFormat describes the format of an instruction encoding. +// An instruction with 32-bit value x matches the format if x&mask == value +// and the predicator: canDecode(x) return true. +type instFormat struct { + mask uint32 + value uint32 + op Op + // args describe how to decode the instruction arguments. + // args is stored as a fixed-size array. + // if there are fewer than len(args) arguments, args[i] == 0 marks + // the end of the argument list. + args instArgs + canDecode func(instr uint32) bool +} + +var ( + errShort = fmt.Errorf("truncated instruction") + errUnknown = fmt.Errorf("unknown instruction") +) + +var decoderCover []bool + +func init() { + decoderCover = make([]bool, len(instFormats)) +} + +// Decode decodes the 4 bytes in src as a single instruction. +func Decode(src []byte) (inst Inst, err error) { + if len(src) < 4 { + return Inst{}, errShort + } + + x := binary.LittleEndian.Uint32(src) + +Search: + for i := range instFormats { + f := &instFormats[i] + if x&f.mask != f.value { + continue + } + if f.canDecode != nil && !f.canDecode(x) { + continue + } + // Decode args. + var args Args + for j, aop := range f.args { + if aop == 0 { + break + } + arg := decodeArg(aop, x) + if arg == nil { // Cannot decode argument + continue Search + } + args[j] = arg + } + decoderCover[i] = true + inst = Inst{ + Op: f.op, + Args: args, + Enc: x, + } + return inst, nil + } + return Inst{}, errUnknown +} + +// decodeArg decodes the arg described by aop from the instruction bits x. +// It returns nil if x cannot be decoded according to aop. +func decodeArg(aop instArg, x uint32) Arg { + switch aop { + default: + return nil + + case arg_Da: + return D0 + Reg((x>>10)&(1<<5-1)) + + case arg_Dd: + return D0 + Reg(x&(1<<5-1)) + + case arg_Dm: + return D0 + Reg((x>>16)&(1<<5-1)) + + case arg_Dn: + return D0 + Reg((x>>5)&(1<<5-1)) + + case arg_Hd: + return H0 + Reg(x&(1<<5-1)) + + case arg_Hn: + return H0 + Reg((x>>5)&(1<<5-1)) + + case arg_IAddSub: + imm12 := (x >> 10) & (1<<12 - 1) + shift := (x >> 22) & (1<<2 - 1) + if shift > 1 { + return nil + } + shift = shift * 12 + return ImmShift{uint16(imm12), uint8(shift)} + + case arg_Sa: + return S0 + Reg((x>>10)&(1<<5-1)) + + case arg_Sd: + return S0 + Reg(x&(1<<5-1)) + + case arg_Sm: + return S0 + Reg((x>>16)&(1<<5-1)) + + case arg_Sn: + return S0 + Reg((x>>5)&(1<<5-1)) + + case arg_Wa: + return W0 + Reg((x>>10)&(1<<5-1)) + + case arg_Wd: + return W0 + Reg(x&(1<<5-1)) + + case arg_Wds: + return RegSP(W0) + RegSP(x&(1<<5-1)) + + case arg_Wm: + return W0 + Reg((x>>16)&(1<<5-1)) + + case arg_Rm_extend__UXTB_0__UXTH_1__UXTW_2__LSL_UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4: + return handle_ExtendedRegister(x, true) + + case arg_Wm_extend__UXTB_0__UXTH_1__LSL_UXTW_2__UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4: + return handle_ExtendedRegister(x, false) + + case arg_Wn: + return W0 + Reg((x>>5)&(1<<5-1)) + + case arg_Wns: + return RegSP(W0) + RegSP((x>>5)&(1<<5-1)) + + case arg_Xa: + return X0 + Reg((x>>10)&(1<<5-1)) + + case arg_Xd: + return X0 + Reg(x&(1<<5-1)) + + case arg_Xds: + return RegSP(X0) + RegSP(x&(1<<5-1)) + + case arg_Xm: + return X0 + Reg((x>>16)&(1<<5-1)) + + case arg_Wm_shift__LSL_0__LSR_1__ASR_2__0_31: + return handle_ImmediateShiftedRegister(x, 31, true, false) + + case arg_Wm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_31: + return handle_ImmediateShiftedRegister(x, 31, true, true) + + case arg_Xm_shift__LSL_0__LSR_1__ASR_2__0_63: + return handle_ImmediateShiftedRegister(x, 63, false, false) + + case arg_Xm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_63: + return handle_ImmediateShiftedRegister(x, 63, false, true) + + case arg_Xn: + return X0 + Reg((x>>5)&(1<<5-1)) + + case arg_Xns: + return RegSP(X0) + RegSP((x>>5)&(1<<5-1)) + + case arg_slabel_imm14_2: + imm14 := ((x >> 5) & (1<<14 - 1)) + return PCRel(((int64(imm14) << 2) << 48) >> 48) + + case arg_slabel_imm19_2: + imm19 := ((x >> 5) & (1<<19 - 1)) + return PCRel(((int64(imm19) << 2) << 43) >> 43) + + case arg_slabel_imm26_2: + imm26 := (x & (1<<26 - 1)) + return PCRel(((int64(imm26) << 2) << 36) >> 36) + + case arg_slabel_immhi_immlo_0: + immhi := ((x >> 5) & (1<<19 - 1)) + immlo := ((x >> 29) & (1<<2 - 1)) + immhilo := (immhi)<<2 | immlo + return PCRel((int64(immhilo) << 43) >> 43) + + case arg_slabel_immhi_immlo_12: + immhi := ((x >> 5) & (1<<19 - 1)) + immlo := ((x >> 29) & (1<<2 - 1)) + immhilo := (immhi)<<2 | immlo + return PCRel(((int64(immhilo) << 12) << 31) >> 31) + + case arg_Xns_mem: + Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1)) + return MemImmediate{Rn, AddrOffset, 0} + + case arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__1_1: + return handle_MemExtend(x, 1, false) + + case arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__2_1: + return handle_MemExtend(x, 2, false) + + case arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__3_1: + return handle_MemExtend(x, 3, false) + + case arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__absent_0__0_1: + return handle_MemExtend(x, 1, true) + + case arg_Xns_mem_optional_imm12_1_unsigned: + Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1)) + imm12 := (x >> 10) & (1<<12 - 1) + return MemImmediate{Rn, AddrOffset, int32(imm12)} + + case arg_Xns_mem_optional_imm12_2_unsigned: + Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1)) + imm12 := (x >> 10) & (1<<12 - 1) + return MemImmediate{Rn, AddrOffset, int32(imm12 << 1)} + + case arg_Xns_mem_optional_imm12_4_unsigned: + Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1)) + imm12 := (x >> 10) & (1<<12 - 1) + return MemImmediate{Rn, AddrOffset, int32(imm12 << 2)} + + case arg_Xns_mem_optional_imm12_8_unsigned: + Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1)) + imm12 := (x >> 10) & (1<<12 - 1) + return MemImmediate{Rn, AddrOffset, int32(imm12 << 3)} + + case arg_Xns_mem_optional_imm7_4_signed: + Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1)) + imm7 := (x >> 15) & (1<<7 - 1) + return MemImmediate{Rn, AddrOffset, ((int32(imm7 << 2)) << 23) >> 23} + + case arg_Xns_mem_optional_imm7_8_signed: + Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1)) + imm7 := (x >> 15) & (1<<7 - 1) + return MemImmediate{Rn, AddrOffset, ((int32(imm7 << 3)) << 22) >> 22} + + case arg_Xns_mem_optional_imm9_1_signed: + Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1)) + imm9 := (x >> 12) & (1<<9 - 1) + return MemImmediate{Rn, AddrOffset, (int32(imm9) << 23) >> 23} + + case arg_Xns_mem_post_imm7_4_signed: + Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1)) + imm7 := (x >> 15) & (1<<7 - 1) + return MemImmediate{Rn, AddrPostIndex, ((int32(imm7 << 2)) << 23) >> 23} + + case arg_Xns_mem_post_imm7_8_signed: + Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1)) + imm7 := (x >> 15) & (1<<7 - 1) + return MemImmediate{Rn, AddrPostIndex, ((int32(imm7 << 3)) << 22) >> 22} + + case arg_Xns_mem_post_imm9_1_signed: + Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1)) + imm9 := (x >> 12) & (1<<9 - 1) + return MemImmediate{Rn, AddrPostIndex, ((int32(imm9)) << 23) >> 23} + + case arg_Xns_mem_wb_imm7_4_signed: + Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1)) + imm7 := (x >> 15) & (1<<7 - 1) + return MemImmediate{Rn, AddrPreIndex, ((int32(imm7 << 2)) << 23) >> 23} + + case arg_Xns_mem_wb_imm7_8_signed: + Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1)) + imm7 := (x >> 15) & (1<<7 - 1) + return MemImmediate{Rn, AddrPreIndex, ((int32(imm7 << 3)) << 22) >> 22} + + case arg_Xns_mem_wb_imm9_1_signed: + Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1)) + imm9 := (x >> 12) & (1<<9 - 1) + return MemImmediate{Rn, AddrPreIndex, ((int32(imm9)) << 23) >> 23} + + case arg_Ws: + return W0 + Reg((x>>16)&(1<<5-1)) + + case arg_Wt: + return W0 + Reg(x&(1<<5-1)) + + case arg_Wt2: + return W0 + Reg((x>>10)&(1<<5-1)) + + case arg_Xs: + return X0 + Reg((x>>16)&(1<<5-1)) + + case arg_Xt: + return X0 + Reg(x&(1<<5-1)) + + case arg_Xt2: + return X0 + Reg((x>>10)&(1<<5-1)) + + case arg_immediate_0_127_CRm_op2: + crm_op2 := (x >> 5) & (1<<7 - 1) + return Imm_hint(crm_op2) + + case arg_immediate_0_15_CRm: + crm := (x >> 8) & (1<<4 - 1) + return Imm{crm, false} + + case arg_immediate_0_15_nzcv: + nzcv := x & (1<<4 - 1) + return Imm{nzcv, false} + + case arg_immediate_0_31_imm5: + imm5 := (x >> 16) & (1<<5 - 1) + return Imm{imm5, false} + + case arg_immediate_0_31_immr: + immr := (x >> 16) & (1<<6 - 1) + if immr > 31 { + return nil + } + return Imm{immr, false} + + case arg_immediate_0_31_imms: + imms := (x >> 10) & (1<<6 - 1) + if imms > 31 { + return nil + } + return Imm{imms, true} + + case arg_immediate_0_63_b5_b40: + b5 := (x >> 31) & 1 + b40 := (x >> 19) & (1<<5 - 1) + return Imm{(b5 << 5) | b40, true} + + case arg_immediate_0_63_immr: + immr := (x >> 16) & (1<<6 - 1) + return Imm{immr, false} + + case arg_immediate_0_63_imms: + imms := (x >> 10) & (1<<6 - 1) + return Imm{imms, true} + + case arg_immediate_0_65535_imm16: + imm16 := (x >> 5) & (1<<16 - 1) + return Imm{imm16, false} + + case arg_immediate_0_7_op1: + op1 := (x >> 16) & (1<<3 - 1) + return Imm{op1, true} + + case arg_immediate_0_7_op2: + op2 := (x >> 5) & (1<<3 - 1) + return Imm{op2, true} + + case arg_immediate_ASR_SBFM_32M_bitfield_0_31_immr: + immr := (x >> 16) & (1<<6 - 1) + if immr > 31 { + return nil + } + return Imm{immr, true} + + case arg_immediate_ASR_SBFM_64M_bitfield_0_63_immr: + immr := (x >> 16) & (1<<6 - 1) + return Imm{immr, true} + + case arg_immediate_BFI_BFM_32M_bitfield_lsb_32_immr: + immr := (x >> 16) & (1<<6 - 1) + if immr > 31 { + return nil + } + return Imm{32 - immr, true} + + case arg_immediate_BFI_BFM_32M_bitfield_width_32_imms: + imms := (x >> 10) & (1<<6 - 1) + if imms > 31 { + return nil + } + return Imm{imms + 1, true} + + case arg_immediate_BFI_BFM_64M_bitfield_lsb_64_immr: + immr := (x >> 16) & (1<<6 - 1) + return Imm{64 - immr, true} + + case arg_immediate_BFI_BFM_64M_bitfield_width_64_imms: + imms := (x >> 10) & (1<<6 - 1) + return Imm{imms + 1, true} + + case arg_immediate_BFXIL_BFM_32M_bitfield_lsb_32_immr: + immr := (x >> 16) & (1<<6 - 1) + if immr > 31 { + return nil + } + return Imm{immr, true} + + case arg_immediate_BFXIL_BFM_32M_bitfield_width_32_imms: + immr := (x >> 16) & (1<<6 - 1) + imms := (x >> 10) & (1<<6 - 1) + width := imms - immr + 1 + if width < 1 || width > 32-immr { + return nil + } + return Imm{width, true} + + case arg_immediate_BFXIL_BFM_64M_bitfield_lsb_64_immr: + immr := (x >> 16) & (1<<6 - 1) + return Imm{immr, true} + + case arg_immediate_BFXIL_BFM_64M_bitfield_width_64_imms: + immr := (x >> 16) & (1<<6 - 1) + imms := (x >> 10) & (1<<6 - 1) + width := imms - immr + 1 + if width < 1 || width > 64-immr { + return nil + } + return Imm{width, true} + + case arg_immediate_bitmask_32_imms_immr: + return handle_bitmasks(x, 32) + + case arg_immediate_bitmask_64_N_imms_immr: + return handle_bitmasks(x, 64) + + case arg_immediate_LSL_UBFM_32M_bitfield_0_31_immr: + imms := (x >> 10) & (1<<6 - 1) + shift := 31 - imms + if shift > 31 { + return nil + } + return Imm{shift, true} + + case arg_immediate_LSL_UBFM_64M_bitfield_0_63_immr: + imms := (x >> 10) & (1<<6 - 1) + shift := 63 - imms + if shift > 63 { + return nil + } + return Imm{shift, true} + + case arg_immediate_LSR_UBFM_32M_bitfield_0_31_immr: + immr := (x >> 16) & (1<<6 - 1) + if immr > 31 { + return nil + } + return Imm{immr, true} + + case arg_immediate_LSR_UBFM_64M_bitfield_0_63_immr: + immr := (x >> 16) & (1<<6 - 1) + return Imm{immr, true} + + case arg_immediate_optional_0_15_CRm: + crm := (x >> 8) & (1<<4 - 1) + return Imm_clrex(crm) + + case arg_immediate_optional_0_65535_imm16: + imm16 := (x >> 5) & (1<<16 - 1) + return Imm_dcps(imm16) + + case arg_immediate_OptLSL_amount_16_0_16: + imm16 := (x >> 5) & (1<<16 - 1) + hw := (x >> 21) & (1<<2 - 1) + shift := hw * 16 + if shift > 16 { + return nil + } + return ImmShift{uint16(imm16), uint8(shift)} + + case arg_immediate_OptLSL_amount_16_0_48: + imm16 := (x >> 5) & (1<<16 - 1) + hw := (x >> 21) & (1<<2 - 1) + shift := hw * 16 + return ImmShift{uint16(imm16), uint8(shift)} + + case arg_immediate_SBFIZ_SBFM_32M_bitfield_lsb_32_immr: + immr := (x >> 16) & (1<<6 - 1) + if immr > 31 { + return nil + } + return Imm{32 - immr, true} + + case arg_immediate_SBFIZ_SBFM_32M_bitfield_width_32_imms: + imms := (x >> 10) & (1<<6 - 1) + if imms > 31 { + return nil + } + return Imm{imms + 1, true} + + case arg_immediate_SBFIZ_SBFM_64M_bitfield_lsb_64_immr: + immr := (x >> 16) & (1<<6 - 1) + return Imm{64 - immr, true} + + case arg_immediate_SBFIZ_SBFM_64M_bitfield_width_64_imms: + imms := (x >> 10) & (1<<6 - 1) + return Imm{imms + 1, true} + + case arg_immediate_SBFX_SBFM_32M_bitfield_lsb_32_immr: + immr := (x >> 16) & (1<<6 - 1) + if immr > 31 { + return nil + } + return Imm{immr, true} + + case arg_immediate_SBFX_SBFM_32M_bitfield_width_32_imms: + immr := (x >> 16) & (1<<6 - 1) + imms := (x >> 10) & (1<<6 - 1) + width := imms - immr + 1 + if width < 1 || width > 32-immr { + return nil + } + return Imm{width, true} + + case arg_immediate_SBFX_SBFM_64M_bitfield_lsb_64_immr: + immr := (x >> 16) & (1<<6 - 1) + return Imm{immr, true} + + case arg_immediate_SBFX_SBFM_64M_bitfield_width_64_imms: + immr := (x >> 16) & (1<<6 - 1) + imms := (x >> 10) & (1<<6 - 1) + width := imms - immr + 1 + if width < 1 || width > 64-immr { + return nil + } + return Imm{width, true} + + case arg_immediate_shift_32_implicit_imm16_hw: + imm16 := (x >> 5) & (1<<16 - 1) + hw := (x >> 21) & (1<<2 - 1) + shift := hw * 16 + if shift > 16 { + return nil + } + result := uint32(imm16) << shift + return Imm{result, false} + + case arg_immediate_shift_32_implicit_inverse_imm16_hw: + imm16 := (x >> 5) & (1<<16 - 1) + hw := (x >> 21) & (1<<2 - 1) + shift := hw * 16 + if shift > 16 { + return nil + } + result := uint32(imm16) << shift + return Imm{^result, false} + + case arg_immediate_shift_64_implicit_imm16_hw: + imm16 := (x >> 5) & (1<<16 - 1) + hw := (x >> 21) & (1<<2 - 1) + shift := hw * 16 + result := uint64(imm16) << shift + return Imm64{result, false} + + case arg_immediate_shift_64_implicit_inverse_imm16_hw: + imm16 := (x >> 5) & (1<<16 - 1) + hw := (x >> 21) & (1<<2 - 1) + shift := hw * 16 + result := uint64(imm16) << shift + return Imm64{^result, false} + + case arg_immediate_UBFIZ_UBFM_32M_bitfield_lsb_32_immr: + immr := (x >> 16) & (1<<6 - 1) + if immr > 31 { + return nil + } + return Imm{32 - immr, true} + + case arg_immediate_UBFIZ_UBFM_32M_bitfield_width_32_imms: + imms := (x >> 10) & (1<<6 - 1) + if imms > 31 { + return nil + } + return Imm{imms + 1, true} + + case arg_immediate_UBFIZ_UBFM_64M_bitfield_lsb_64_immr: + immr := (x >> 16) & (1<<6 - 1) + return Imm{64 - immr, true} + + case arg_immediate_UBFIZ_UBFM_64M_bitfield_width_64_imms: + imms := (x >> 10) & (1<<6 - 1) + return Imm{imms + 1, true} + + case arg_immediate_UBFX_UBFM_32M_bitfield_lsb_32_immr: + immr := (x >> 16) & (1<<6 - 1) + if immr > 31 { + return nil + } + return Imm{immr, true} + + case arg_immediate_UBFX_UBFM_32M_bitfield_width_32_imms: + immr := (x >> 16) & (1<<6 - 1) + imms := (x >> 10) & (1<<6 - 1) + width := imms - immr + 1 + if width < 1 || width > 32-immr { + return nil + } + return Imm{width, true} + + case arg_immediate_UBFX_UBFM_64M_bitfield_lsb_64_immr: + immr := (x >> 16) & (1<<6 - 1) + return Imm{immr, true} + + case arg_immediate_UBFX_UBFM_64M_bitfield_width_64_imms: + immr := (x >> 16) & (1<<6 - 1) + imms := (x >> 10) & (1<<6 - 1) + width := imms - immr + 1 + if width < 1 || width > 64-immr { + return nil + } + return Imm{width, true} + + case arg_Rt_31_1__W_0__X_1: + b5 := (x >> 31) & 1 + Rt := x & (1<<5 - 1) + if b5 == 0 { + return W0 + Reg(Rt) + } else { + return X0 + Reg(Rt) + } + + case arg_cond_AllowALNV_Normal: + cond := (x >> 12) & (1<<4 - 1) + return Cond{uint8(cond), false} + + case arg_conditional: + cond := x & (1<<4 - 1) + return Cond{uint8(cond), false} + + case arg_cond_NotAllowALNV_Invert: + cond := (x >> 12) & (1<<4 - 1) + if (cond >> 1) == 7 { + return nil + } + return Cond{uint8(cond), true} + + case arg_Cm: + CRm := (x >> 8) & (1<<4 - 1) + return Imm_c(CRm) + + case arg_Cn: + CRn := (x >> 12) & (1<<4 - 1) + return Imm_c(CRn) + + case arg_option_DMB_BO_system_CRm: + CRm := (x >> 8) & (1<<4 - 1) + return Imm_option(CRm) + + case arg_option_DSB_BO_system_CRm: + CRm := (x >> 8) & (1<<4 - 1) + return Imm_option(CRm) + + case arg_option_ISB_BI_system_CRm: + CRm := (x >> 8) & (1<<4 - 1) + if CRm == 15 { + return Imm_option(CRm) + } + return Imm{CRm, false} + + case arg_prfop_Rt: + Rt := x & (1<<5 - 1) + return Imm_prfop(Rt) + + case arg_pstatefield_op1_op2__SPSel_05__DAIFSet_36__DAIFClr_37: + op1 := (x >> 16) & (1<<3 - 1) + op2 := (x >> 5) & (1<<3 - 1) + if (op1 == 0) && (op2 == 5) { + return SPSel + } else if (op1 == 3) && (op2 == 6) { + return DAIFSet + } else if (op1 == 3) && (op2 == 7) { + return DAIFClr + } + return nil + + case arg_sysreg_o0_op1_CRn_CRm_op2: + op0 := (x >> 19) & (1<<2 - 1) + op1 := (x >> 16) & (1<<3 - 1) + CRn := (x >> 12) & (1<<4 - 1) + CRm := (x >> 8) & (1<<4 - 1) + op2 := (x >> 5) & (1<<3 - 1) + return Systemreg{uint8(op0), uint8(op1), uint8(CRn), uint8(CRm), uint8(op2)} + + case arg_sysop_AT_SYS_CR_system: + //TODO: system instruction + return nil + + case arg_sysop_DC_SYS_CR_system: + //TODO: system instruction + return nil + + case arg_sysop_SYS_CR_system: + //TODO: system instruction + return nil + + case arg_sysop_TLBI_SYS_CR_system: + //TODO: system instruction + return nil + + case arg_Bt: + return B0 + Reg(x&(1<<5-1)) + + case arg_Dt: + return D0 + Reg(x&(1<<5-1)) + + case arg_Dt2: + return D0 + Reg((x>>10)&(1<<5-1)) + + case arg_Ht: + return H0 + Reg(x&(1<<5-1)) + + case arg_immediate_0_63_immh_immb__UIntimmhimmb64_8: + immh := (x >> 19) & (1<<4 - 1) + if (immh & 8) == 0 { + return nil + } + immb := (x >> 16) & (1<<3 - 1) + return Imm{(immh << 3) + immb - 64, true} + + case arg_immediate_0_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4: + immh := (x >> 19) & (1<<4 - 1) + immb := (x >> 16) & (1<<3 - 1) + if immh == 1 { + return Imm{(immh << 3) + immb - 8, true} + } else if (immh >> 1) == 1 { + return Imm{(immh << 3) + immb - 16, true} + } else if (immh >> 2) == 1 { + return Imm{(immh << 3) + immb - 32, true} + } else { + return nil + } + + case arg_immediate_0_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4__UIntimmhimmb64_8: + fallthrough + + case arg_immediate_0_width_m1_immh_immb__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4__UIntimmhimmb64_8: + immh := (x >> 19) & (1<<4 - 1) + immb := (x >> 16) & (1<<3 - 1) + if immh == 1 { + return Imm{(immh << 3) + immb - 8, true} + } else if (immh >> 1) == 1 { + return Imm{(immh << 3) + immb - 16, true} + } else if (immh >> 2) == 1 { + return Imm{(immh << 3) + immb - 32, true} + } else if (immh >> 3) == 1 { + return Imm{(immh << 3) + immb - 64, true} + } else { + return nil + } + + case arg_immediate_0_width_size__8_0__16_1__32_2: + size := (x >> 22) & (1<<2 - 1) + switch size { + case 0: + return Imm{8, true} + case 1: + return Imm{16, true} + case 2: + return Imm{32, true} + default: + return nil + } + + case arg_immediate_1_64_immh_immb__128UIntimmhimmb_8: + immh := (x >> 19) & (1<<4 - 1) + if (immh & 8) == 0 { + return nil + } + immb := (x >> 16) & (1<<3 - 1) + return Imm{128 - ((immh << 3) + immb), true} + + case arg_immediate_1_width_immh_immb__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4: + fallthrough + + case arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4: + immh := (x >> 19) & (1<<4 - 1) + immb := (x >> 16) & (1<<3 - 1) + if immh == 1 { + return Imm{16 - ((immh << 3) + immb), true} + } else if (immh >> 1) == 1 { + return Imm{32 - ((immh << 3) + immb), true} + } else if (immh >> 2) == 1 { + return Imm{64 - ((immh << 3) + immb), true} + } else { + return nil + } + + case arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4__128UIntimmhimmb_8: + immh := (x >> 19) & (1<<4 - 1) + immb := (x >> 16) & (1<<3 - 1) + if immh == 1 { + return Imm{16 - ((immh << 3) + immb), true} + } else if (immh >> 1) == 1 { + return Imm{32 - ((immh << 3) + immb), true} + } else if (immh >> 2) == 1 { + return Imm{64 - ((immh << 3) + immb), true} + } else if (immh >> 3) == 1 { + return Imm{128 - ((immh << 3) + immb), true} + } else { + return nil + } + + case arg_immediate_8x8_a_b_c_d_e_f_g_h: + var imm uint64 + if x&(1<<5) != 0 { + imm = (1 << 8) - 1 + } else { + imm = 0 + } + if x&(1<<6) != 0 { + imm += ((1 << 8) - 1) << 8 + } + if x&(1<<7) != 0 { + imm += ((1 << 8) - 1) << 16 + } + if x&(1<<8) != 0 { + imm += ((1 << 8) - 1) << 24 + } + if x&(1<<9) != 0 { + imm += ((1 << 8) - 1) << 32 + } + if x&(1<<16) != 0 { + imm += ((1 << 8) - 1) << 40 + } + if x&(1<<17) != 0 { + imm += ((1 << 8) - 1) << 48 + } + if x&(1<<18) != 0 { + imm += ((1 << 8) - 1) << 56 + } + return Imm64{imm, false} + + case arg_immediate_exp_3_pre_4_a_b_c_d_e_f_g_h: + pre := (x >> 5) & (1<<4 - 1) + exp := 1 - ((x >> 17) & 1) + exp = (exp << 2) + (((x >> 16) & 1) << 1) + ((x >> 9) & 1) + s := ((x >> 18) & 1) + return Imm_fp{uint8(s), int8(exp) - 3, uint8(pre)} + + case arg_immediate_exp_3_pre_4_imm8: + pre := (x >> 13) & (1<<4 - 1) + exp := 1 - ((x >> 19) & 1) + exp = (exp << 2) + ((x >> 17) & (1<<2 - 1)) + s := ((x >> 20) & 1) + return Imm_fp{uint8(s), int8(exp) - 3, uint8(pre)} + + case arg_immediate_fbits_min_1_max_0_sub_0_immh_immb__64UIntimmhimmb_4__128UIntimmhimmb_8: + fallthrough + + case arg_immediate_fbits_min_1_max_0_sub_0_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__64UIntimmhimmb_4__128UIntimmhimmb_8: + immh := (x >> 19) & (1<<4 - 1) + immb := (x >> 16) & (1<<3 - 1) + if (immh >> 2) == 1 { + return Imm{64 - ((immh << 3) + immb), true} + } else if (immh >> 3) == 1 { + return Imm{128 - ((immh << 3) + immb), true} + } else { + return nil + } + + case arg_immediate_fbits_min_1_max_32_sub_64_scale: + scale := (x >> 10) & (1<<6 - 1) + fbits := 64 - scale + if fbits > 32 { + return nil + } + return Imm{fbits, true} + + case arg_immediate_fbits_min_1_max_64_sub_64_scale: + scale := (x >> 10) & (1<<6 - 1) + fbits := 64 - scale + return Imm{fbits, true} + + case arg_immediate_floatzero: + return Imm{0, true} + + case arg_immediate_index_Q_imm4__imm4lt20gt_00__imm4_10: + Q := (x >> 30) & 1 + imm4 := (x >> 11) & (1<<4 - 1) + if Q == 1 || (imm4>>3) == 0 { + return Imm{imm4, true} + } else { + return nil + } + + case arg_immediate_MSL__a_b_c_d_e_f_g_h_cmode__8_0__16_1: + var shift uint8 + imm8 := (x >> 16) & (1<<3 - 1) + imm8 = (imm8 << 5) | ((x >> 5) & (1<<5 - 1)) + if (x>>12)&1 == 0 { + shift = 8 + 128 + } else { + shift = 16 + 128 + } + return ImmShift{uint16(imm8), shift} + + case arg_immediate_OptLSL__a_b_c_d_e_f_g_h_cmode__0_0__8_1: + imm8 := (x >> 16) & (1<<3 - 1) + imm8 = (imm8 << 5) | ((x >> 5) & (1<<5 - 1)) + cmode1 := (x >> 13) & 1 + shift := 8 * cmode1 + return ImmShift{uint16(imm8), uint8(shift)} + + case arg_immediate_OptLSL__a_b_c_d_e_f_g_h_cmode__0_0__8_1__16_2__24_3: + imm8 := (x >> 16) & (1<<3 - 1) + imm8 = (imm8 << 5) | ((x >> 5) & (1<<5 - 1)) + cmode1 := (x >> 13) & (1<<2 - 1) + shift := 8 * cmode1 + return ImmShift{uint16(imm8), uint8(shift)} + + case arg_immediate_OptLSLZero__a_b_c_d_e_f_g_h: + imm8 := (x >> 16) & (1<<3 - 1) + imm8 = (imm8 << 5) | ((x >> 5) & (1<<5 - 1)) + return ImmShift{uint16(imm8), 0} + + case arg_immediate_zero: + return Imm{0, true} + + case arg_Qd: + return Q0 + Reg(x&(1<<5-1)) + + case arg_Qn: + return Q0 + Reg((x>>5)&(1<<5-1)) + + case arg_Qt: + return Q0 + Reg(x&(1<<5-1)) + + case arg_Qt2: + return Q0 + Reg((x>>10)&(1<<5-1)) + + case arg_Rn_16_5__W_1__W_2__W_4__X_8: + imm5 := (x >> 16) & (1<<5 - 1) + if ((imm5 & 1) == 1) || ((imm5 & 2) == 2) || ((imm5 & 4) == 4) { + return W0 + Reg((x>>5)&(1<<5-1)) + } else if (imm5 & 8) == 8 { + return X0 + Reg((x>>5)&(1<<5-1)) + } else { + return nil + } + + case arg_St: + return S0 + Reg(x&(1<<5-1)) + + case arg_St2: + return S0 + Reg((x>>10)&(1<<5-1)) + + case arg_Vd_16_5__B_1__H_2__S_4__D_8: + imm5 := (x >> 16) & (1<<5 - 1) + Rd := x & (1<<5 - 1) + if imm5&1 == 1 { + return B0 + Reg(Rd) + } else if imm5&2 == 2 { + return H0 + Reg(Rd) + } else if imm5&4 == 4 { + return S0 + Reg(Rd) + } else if imm5&8 == 8 { + return D0 + Reg(Rd) + } else { + return nil + } + + case arg_Vd_19_4__B_1__H_2__S_4: + immh := (x >> 19) & (1<<4 - 1) + Rd := x & (1<<5 - 1) + if immh == 1 { + return B0 + Reg(Rd) + } else if immh>>1 == 1 { + return H0 + Reg(Rd) + } else if immh>>2 == 1 { + return S0 + Reg(Rd) + } else { + return nil + } + + case arg_Vd_19_4__B_1__H_2__S_4__D_8: + immh := (x >> 19) & (1<<4 - 1) + Rd := x & (1<<5 - 1) + if immh == 1 { + return B0 + Reg(Rd) + } else if immh>>1 == 1 { + return H0 + Reg(Rd) + } else if immh>>2 == 1 { + return S0 + Reg(Rd) + } else if immh>>3 == 1 { + return D0 + Reg(Rd) + } else { + return nil + } + + case arg_Vd_19_4__D_8: + immh := (x >> 19) & (1<<4 - 1) + Rd := x & (1<<5 - 1) + if immh>>3 == 1 { + return D0 + Reg(Rd) + } else { + return nil + } + + case arg_Vd_19_4__S_4__D_8: + immh := (x >> 19) & (1<<4 - 1) + Rd := x & (1<<5 - 1) + if immh>>2 == 1 { + return S0 + Reg(Rd) + } else if immh>>3 == 1 { + return D0 + Reg(Rd) + } else { + return nil + } + + case arg_Vd_22_1__S_0: + sz := (x >> 22) & 1 + Rd := x & (1<<5 - 1) + if sz == 0 { + return S0 + Reg(Rd) + } else { + return nil + } + + case arg_Vd_22_1__S_0__D_1: + sz := (x >> 22) & 1 + Rd := x & (1<<5 - 1) + if sz == 0 { + return S0 + Reg(Rd) + } else { + return D0 + Reg(Rd) + } + + case arg_Vd_22_1__S_1: + sz := (x >> 22) & 1 + Rd := x & (1<<5 - 1) + if sz == 1 { + return S0 + Reg(Rd) + } else { + return nil + } + + case arg_Vd_22_2__B_0__H_1__S_2: + size := (x >> 22) & (1<<2 - 1) + Rd := x & (1<<5 - 1) + if size == 0 { + return B0 + Reg(Rd) + } else if size == 1 { + return H0 + Reg(Rd) + } else if size == 2 { + return S0 + Reg(Rd) + } else { + return nil + } + + case arg_Vd_22_2__B_0__H_1__S_2__D_3: + size := (x >> 22) & (1<<2 - 1) + Rd := x & (1<<5 - 1) + if size == 0 { + return B0 + Reg(Rd) + } else if size == 1 { + return H0 + Reg(Rd) + } else if size == 2 { + return S0 + Reg(Rd) + } else { + return D0 + Reg(Rd) + } + + case arg_Vd_22_2__D_3: + size := (x >> 22) & (1<<2 - 1) + Rd := x & (1<<5 - 1) + if size == 3 { + return D0 + Reg(Rd) + } else { + return nil + } + + case arg_Vd_22_2__H_0__S_1__D_2: + size := (x >> 22) & (1<<2 - 1) + Rd := x & (1<<5 - 1) + if size == 0 { + return H0 + Reg(Rd) + } else if size == 1 { + return S0 + Reg(Rd) + } else if size == 2 { + return D0 + Reg(Rd) + } else { + return nil + } + + case arg_Vd_22_2__H_1__S_2: + size := (x >> 22) & (1<<2 - 1) + Rd := x & (1<<5 - 1) + if size == 1 { + return H0 + Reg(Rd) + } else if size == 2 { + return S0 + Reg(Rd) + } else { + return nil + } + + case arg_Vd_22_2__S_1__D_2: + size := (x >> 22) & (1<<2 - 1) + Rd := x & (1<<5 - 1) + if size == 1 { + return S0 + Reg(Rd) + } else if size == 2 { + return D0 + Reg(Rd) + } else { + return nil + } + + case arg_Vd_arrangement_16B: + Rd := x & (1<<5 - 1) + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement16B, 0} + + case arg_Vd_arrangement_2D: + Rd := x & (1<<5 - 1) + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2D, 0} + + case arg_Vd_arrangement_4S: + Rd := x & (1<<5 - 1) + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0} + + case arg_Vd_arrangement_D_index__1: + Rd := x & (1<<5 - 1) + return RegisterWithArrangementAndIndex{V0 + Reg(Rd), ArrangementD, 1, 0} + + case arg_Vd_arrangement_imm5___B_1__H_2__S_4__D_8_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4__imm5lt4gt_8_1: + var a Arrangement + var index uint32 + Rd := x & (1<<5 - 1) + imm5 := (x >> 16) & (1<<5 - 1) + if imm5&1 == 1 { + a = ArrangementB + index = imm5 >> 1 + } else if imm5&2 == 2 { + a = ArrangementH + index = imm5 >> 2 + } else if imm5&4 == 4 { + a = ArrangementS + index = imm5 >> 3 + } else if imm5&8 == 8 { + a = ArrangementD + index = imm5 >> 4 + } else { + return nil + } + return RegisterWithArrangementAndIndex{V0 + Reg(Rd), a, uint8(index), 0} + + case arg_Vd_arrangement_imm5_Q___8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81: + Rd := x & (1<<5 - 1) + imm5 := (x >> 16) & (1<<5 - 1) + Q := (x >> 30) & 1 + if imm5&1 == 1 { + if Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8B, 0} + } else { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement16B, 0} + } + } else if imm5&2 == 2 { + if Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4H, 0} + } else { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0} + } + } else if imm5&4 == 4 { + if Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0} + } else { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0} + } + } else if (imm5&8 == 8) && (Q == 1) { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2D, 0} + } else { + return nil + } + + case arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__2S_40__4S_41__2D_81: + Rd := x & (1<<5 - 1) + immh := (x >> 19) & (1<<4 - 1) + Q := (x >> 30) & 1 + if immh>>2 == 1 { + if Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0} + } else { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0} + } + } else if immh>>3 == 1 { + if Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2D, 0} + } + } + return nil + + case arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41: + Rd := x & (1<<5 - 1) + immh := (x >> 19) & (1<<4 - 1) + Q := (x >> 30) & 1 + if immh == 1 { + if Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8B, 0} + } else { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement16B, 0} + } + } else if immh>>1 == 1 { + if Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4H, 0} + } else { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0} + } + } else if immh>>2 == 1 { + if Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0} + } else { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0} + } + } + return nil + + case arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81: + Rd := x & (1<<5 - 1) + immh := (x >> 19) & (1<<4 - 1) + Q := (x >> 30) & 1 + if immh == 1 { + if Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8B, 0} + } else { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement16B, 0} + } + } else if immh>>1 == 1 { + if Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4H, 0} + } else { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0} + } + } else if immh>>2 == 1 { + if Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0} + } else { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0} + } + } else if immh>>3 == 1 { + if Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2D, 0} + } + } + return nil + + case arg_Vd_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4: + Rd := x & (1<<5 - 1) + immh := (x >> 19) & (1<<4 - 1) + if immh == 1 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0} + } else if immh>>1 == 1 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0} + } else if immh>>2 == 1 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2D, 0} + } + return nil + + case arg_Vd_arrangement_Q___2S_0__4S_1: + Rd := x & (1<<5 - 1) + Q := (x >> 30) & 1 + if Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0} + } else { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0} + } + + case arg_Vd_arrangement_Q___4H_0__8H_1: + Rd := x & (1<<5 - 1) + Q := (x >> 30) & 1 + if Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4H, 0} + } else { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0} + } + + case arg_Vd_arrangement_Q___8B_0__16B_1: + Rd := x & (1<<5 - 1) + Q := (x >> 30) & 1 + if Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8B, 0} + } else { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement16B, 0} + } + + case arg_Vd_arrangement_Q_sz___2S_00__4S_10__2D_11: + Rd := x & (1<<5 - 1) + Q := (x >> 30) & 1 + sz := (x >> 22) & 1 + if sz == 0 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0} + } else if sz == 0 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0} + } else if sz == 1 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2D, 0} + } + return nil + + case arg_Vd_arrangement_size___4S_1__2D_2: + Rd := x & (1<<5 - 1) + size := (x >> 22) & 3 + if size == 1 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0} + } else if size == 2 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2D, 0} + } + return nil + + case arg_Vd_arrangement_size___8H_0__1Q_3: + Rd := x & (1<<5 - 1) + size := (x >> 22) & 3 + if size == 0 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0} + } else if size == 3 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement1Q, 0} + } + return nil + + case arg_Vd_arrangement_size___8H_0__4S_1__2D_2: + Rd := x & (1<<5 - 1) + size := (x >> 22) & 3 + if size == 0 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0} + } else if size == 1 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0} + } else if size == 2 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2D, 0} + } + return nil + + case arg_Vd_arrangement_size_Q___4H_00__8H_01__2S_10__4S_11__1D_20__2D_21: + Rd := x & (1<<5 - 1) + size := (x >> 22) & 3 + Q := (x >> 30) & 1 + if size == 0 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4H, 0} + } else if size == 0 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0} + } else if size == 1 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0} + } else if size == 1 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0} + } else if size == 2 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement1D, 0} + } else if size == 2 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2D, 0} + } + return nil + + case arg_Vd_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21: + Rd := x & (1<<5 - 1) + size := (x >> 22) & 3 + Q := (x >> 30) & 1 + if size == 1 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4H, 0} + } else if size == 1 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0} + } else if size == 2 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0} + } else if size == 2 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0} + } + return nil + + case arg_Vd_arrangement_size_Q___8B_00__16B_01: + Rd := x & (1<<5 - 1) + size := (x >> 22) & 3 + Q := (x >> 30) & 1 + if size == 0 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8B, 0} + } else if size == 0 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement16B, 0} + } + return nil + + case arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11: + Rd := x & (1<<5 - 1) + size := (x >> 22) & 3 + Q := (x >> 30) & 1 + if size == 0 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8B, 0} + } else if size == 0 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement16B, 0} + } else if size == 1 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4H, 0} + } else if size == 1 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0} + } + return nil + + case arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21: + Rd := x & (1<<5 - 1) + size := (x >> 22) & 3 + Q := (x >> 30) & 1 + if size == 0 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8B, 0} + } else if size == 0 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement16B, 0} + } else if size == 1 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4H, 0} + } else if size == 1 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0} + } else if size == 2 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0} + } else if size == 2 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0} + } + return nil + + case arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31: + Rd := x & (1<<5 - 1) + size := (x >> 22) & 3 + Q := (x >> 30) & 1 + if size == 0 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8B, 0} + } else if size == 0 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement16B, 0} + } else if size == 1 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4H, 0} + } else if size == 1 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0} + } else if size == 2 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0} + } else if size == 2 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0} + } else if size == 3 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2D, 0} + } + return nil + + case arg_Vd_arrangement_sz___4S_0__2D_1: + Rd := x & (1<<5 - 1) + sz := (x >> 22) & 1 + if sz == 0 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0} + } else { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2D, 0} + } + + case arg_Vd_arrangement_sz_Q___2S_00__4S_01: + Rd := x & (1<<5 - 1) + sz := (x >> 22) & 1 + Q := (x >> 30) & 1 + if sz == 0 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0} + } else if sz == 0 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0} + } + return nil + + case arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11: + Rd := x & (1<<5 - 1) + sz := (x >> 22) & 1 + Q := (x >> 30) & 1 + if sz == 0 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0} + } else if sz == 0 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0} + } else if sz == 1 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2D, 0} + } + return nil + + case arg_Vd_arrangement_sz_Q___2S_10__4S_11: + Rd := x & (1<<5 - 1) + sz := (x >> 22) & 1 + Q := (x >> 30) & 1 + if sz == 1 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0} + } else if sz == 1 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0} + } + return nil + + case arg_Vd_arrangement_sz_Q___4H_00__8H_01__2S_10__4S_11: + Rd := x & (1<<5 - 1) + sz := (x >> 22) & 1 + Q := (x >> 30) & 1 + if sz == 0 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4H, 0} + } else if sz == 0 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0} + } else if sz == 1 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0} + } else /* sz == 1 && Q == 1 */ { + return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0} + } + + case arg_Vm_22_1__S_0__D_1: + sz := (x >> 22) & 1 + Rm := (x >> 16) & (1<<5 - 1) + if sz == 0 { + return S0 + Reg(Rm) + } else { + return D0 + Reg(Rm) + } + + case arg_Vm_22_2__B_0__H_1__S_2__D_3: + size := (x >> 22) & (1<<2 - 1) + Rm := (x >> 16) & (1<<5 - 1) + if size == 0 { + return B0 + Reg(Rm) + } else if size == 1 { + return H0 + Reg(Rm) + } else if size == 2 { + return S0 + Reg(Rm) + } else { + return D0 + Reg(Rm) + } + + case arg_Vm_22_2__D_3: + size := (x >> 22) & (1<<2 - 1) + Rm := (x >> 16) & (1<<5 - 1) + if size == 3 { + return D0 + Reg(Rm) + } else { + return nil + } + + case arg_Vm_22_2__H_1__S_2: + size := (x >> 22) & (1<<2 - 1) + Rm := (x >> 16) & (1<<5 - 1) + if size == 1 { + return H0 + Reg(Rm) + } else if size == 2 { + return S0 + Reg(Rm) + } else { + return nil + } + + case arg_Vm_arrangement_4S: + Rm := (x >> 16) & (1<<5 - 1) + return RegisterWithArrangement{V0 + Reg(Rm), Arrangement4S, 0} + + case arg_Vm_arrangement_Q___8B_0__16B_1: + Rm := (x >> 16) & (1<<5 - 1) + Q := (x >> 30) & 1 + if Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rm), Arrangement8B, 0} + } else { + return RegisterWithArrangement{V0 + Reg(Rm), Arrangement16B, 0} + } + + case arg_Vm_arrangement_size___8H_0__4S_1__2D_2: + Rm := (x >> 16) & (1<<5 - 1) + size := (x >> 22) & 3 + if size == 0 { + return RegisterWithArrangement{V0 + Reg(Rm), Arrangement8H, 0} + } else if size == 1 { + return RegisterWithArrangement{V0 + Reg(Rm), Arrangement4S, 0} + } else if size == 2 { + return RegisterWithArrangement{V0 + Reg(Rm), Arrangement2D, 0} + } + return nil + + case arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1: + var a Arrangement + var index uint32 + var vm uint32 + Rm := (x >> 16) & (1<<4 - 1) + size := (x >> 22) & 3 + H := (x >> 11) & 1 + L := (x >> 21) & 1 + M := (x >> 20) & 1 + if size == 1 { + a = ArrangementH + index = (H << 2) | (L << 1) | M + vm = Rm + } else if size == 2 { + a = ArrangementS + index = (H << 1) | L + vm = (M << 4) | Rm + } else { + return nil + } + return RegisterWithArrangementAndIndex{V0 + Reg(vm), a, uint8(index), 0} + + case arg_Vm_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21: + Rm := (x >> 16) & (1<<5 - 1) + size := (x >> 22) & 3 + Q := (x >> 30) & 1 + if size == 1 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rm), Arrangement4H, 0} + } else if size == 1 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rm), Arrangement8H, 0} + } else if size == 2 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rm), Arrangement2S, 0} + } else if size == 2 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rm), Arrangement4S, 0} + } + return nil + + case arg_Vm_arrangement_size_Q___8B_00__16B_01: + Rm := (x >> 16) & (1<<5 - 1) + size := (x >> 22) & 3 + Q := (x >> 30) & 1 + if size == 0 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rm), Arrangement8B, 0} + } else if size == 0 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rm), Arrangement16B, 0} + } + return nil + + case arg_Vm_arrangement_size_Q___8B_00__16B_01__1D_30__2D_31: + Rm := (x >> 16) & (1<<5 - 1) + size := (x >> 22) & 3 + Q := (x >> 30) & 1 + if size == 0 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rm), Arrangement8B, 0} + } else if size == 0 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rm), Arrangement16B, 0} + } else if size == 3 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rm), Arrangement1D, 0} + } else if size == 3 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rm), Arrangement2D, 0} + } + return nil + + case arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21: + Rm := (x >> 16) & (1<<5 - 1) + size := (x >> 22) & 3 + Q := (x >> 30) & 1 + if size == 0 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rm), Arrangement8B, 0} + } else if size == 0 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rm), Arrangement16B, 0} + } else if size == 1 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rm), Arrangement4H, 0} + } else if size == 1 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rm), Arrangement8H, 0} + } else if size == 2 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rm), Arrangement2S, 0} + } else if size == 2 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rm), Arrangement4S, 0} + } + return nil + + case arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31: + Rm := (x >> 16) & (1<<5 - 1) + size := (x >> 22) & 3 + Q := (x >> 30) & 1 + if size == 0 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rm), Arrangement8B, 0} + } else if size == 0 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rm), Arrangement16B, 0} + } else if size == 1 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rm), Arrangement4H, 0} + } else if size == 1 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rm), Arrangement8H, 0} + } else if size == 2 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rm), Arrangement2S, 0} + } else if size == 2 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rm), Arrangement4S, 0} + } else if size == 3 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rm), Arrangement2D, 0} + } + return nil + + case arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11: + Rm := (x >> 16) & (1<<5 - 1) + sz := (x >> 22) & 1 + Q := (x >> 30) & 1 + if sz == 0 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rm), Arrangement2S, 0} + } else if sz == 0 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rm), Arrangement4S, 0} + } else if sz == 1 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rm), Arrangement2D, 0} + } + return nil + + case arg_Vm_arrangement_sz___S_0__D_1_index__sz_L_H__HL_00__H_10_1: + var a Arrangement + var index uint32 + Rm := (x >> 16) & (1<<5 - 1) + sz := (x >> 22) & 1 + H := (x >> 11) & 1 + L := (x >> 21) & 1 + if sz == 0 { + a = ArrangementS + index = (H << 1) | L + } else if sz == 1 && L == 0 { + a = ArrangementD + index = H + } else { + return nil + } + return RegisterWithArrangementAndIndex{V0 + Reg(Rm), a, uint8(index), 0} + + case arg_Vn_19_4__B_1__H_2__S_4__D_8: + immh := (x >> 19) & (1<<4 - 1) + Rn := (x >> 5) & (1<<5 - 1) + if immh == 1 { + return B0 + Reg(Rn) + } else if immh>>1 == 1 { + return H0 + Reg(Rn) + } else if immh>>2 == 1 { + return S0 + Reg(Rn) + } else if immh>>3 == 1 { + return D0 + Reg(Rn) + } else { + return nil + } + + case arg_Vn_19_4__D_8: + immh := (x >> 19) & (1<<4 - 1) + Rn := (x >> 5) & (1<<5 - 1) + if immh>>3 == 1 { + return D0 + Reg(Rn) + } else { + return nil + } + + case arg_Vn_19_4__H_1__S_2__D_4: + immh := (x >> 19) & (1<<4 - 1) + Rn := (x >> 5) & (1<<5 - 1) + if immh == 1 { + return H0 + Reg(Rn) + } else if immh>>1 == 1 { + return S0 + Reg(Rn) + } else if immh>>2 == 1 { + return D0 + Reg(Rn) + } else { + return nil + } + + case arg_Vn_19_4__S_4__D_8: + immh := (x >> 19) & (1<<4 - 1) + Rn := (x >> 5) & (1<<5 - 1) + if immh>>2 == 1 { + return S0 + Reg(Rn) + } else if immh>>3 == 1 { + return D0 + Reg(Rn) + } else { + return nil + } + + case arg_Vn_1_arrangement_16B: + Rn := (x >> 5) & (1<<5 - 1) + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 1} + + case arg_Vn_22_1__D_1: + sz := (x >> 22) & 1 + Rn := (x >> 5) & (1<<5 - 1) + if sz == 1 { + return D0 + Reg(Rn) + } + return nil + + case arg_Vn_22_1__S_0__D_1: + sz := (x >> 22) & 1 + Rn := (x >> 5) & (1<<5 - 1) + if sz == 0 { + return S0 + Reg(Rn) + } else { + return D0 + Reg(Rn) + } + + case arg_Vn_22_2__B_0__H_1__S_2__D_3: + size := (x >> 22) & (1<<2 - 1) + Rn := (x >> 5) & (1<<5 - 1) + if size == 0 { + return B0 + Reg(Rn) + } else if size == 1 { + return H0 + Reg(Rn) + } else if size == 2 { + return S0 + Reg(Rn) + } else { + return D0 + Reg(Rn) + } + + case arg_Vn_22_2__D_3: + size := (x >> 22) & (1<<2 - 1) + Rn := (x >> 5) & (1<<5 - 1) + if size == 3 { + return D0 + Reg(Rn) + } else { + return nil + } + + case arg_Vn_22_2__H_0__S_1__D_2: + size := (x >> 22) & (1<<2 - 1) + Rn := (x >> 5) & (1<<5 - 1) + if size == 0 { + return H0 + Reg(Rn) + } else if size == 1 { + return S0 + Reg(Rn) + } else if size == 2 { + return D0 + Reg(Rn) + } else { + return nil + } + + case arg_Vn_22_2__H_1__S_2: + size := (x >> 22) & (1<<2 - 1) + Rn := (x >> 5) & (1<<5 - 1) + if size == 1 { + return H0 + Reg(Rn) + } else if size == 2 { + return S0 + Reg(Rn) + } else { + return nil + } + + case arg_Vn_2_arrangement_16B: + Rn := (x >> 5) & (1<<5 - 1) + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 2} + + case arg_Vn_3_arrangement_16B: + Rn := (x >> 5) & (1<<5 - 1) + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 3} + + case arg_Vn_4_arrangement_16B: + Rn := (x >> 5) & (1<<5 - 1) + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 4} + + case arg_Vn_arrangement_16B: + Rn := (x >> 5) & (1<<5 - 1) + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 0} + + case arg_Vn_arrangement_4S: + Rn := (x >> 5) & (1<<5 - 1) + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0} + + case arg_Vn_arrangement_D_index__1: + Rn := (x >> 5) & (1<<5 - 1) + return RegisterWithArrangementAndIndex{V0 + Reg(Rn), ArrangementD, 1, 0} + + case arg_Vn_arrangement_D_index__imm5_1: + Rn := (x >> 5) & (1<<5 - 1) + index := (x >> 20) & 1 + return RegisterWithArrangementAndIndex{V0 + Reg(Rn), ArrangementD, uint8(index), 0} + + case arg_Vn_arrangement_imm5___B_1__H_2_index__imm5__imm5lt41gt_1__imm5lt42gt_2_1: + var a Arrangement + var index uint32 + Rn := (x >> 5) & (1<<5 - 1) + imm5 := (x >> 16) & (1<<5 - 1) + if imm5&1 == 1 { + a = ArrangementB + index = imm5 >> 1 + } else if imm5&2 == 2 { + a = ArrangementH + index = imm5 >> 2 + } else { + return nil + } + return RegisterWithArrangementAndIndex{V0 + Reg(Rn), a, uint8(index), 0} + + case arg_Vn_arrangement_imm5___B_1__H_2__S_4__D_8_index__imm5_imm4__imm4lt30gt_1__imm4lt31gt_2__imm4lt32gt_4__imm4lt3gt_8_1: + var a Arrangement + var index uint32 + Rn := (x >> 5) & (1<<5 - 1) + imm5 := (x >> 16) & (1<<5 - 1) + imm4 := (x >> 11) & (1<<4 - 1) + if imm5&1 == 1 { + a = ArrangementB + index = imm4 + } else if imm5&2 == 2 { + a = ArrangementH + index = imm4 >> 1 + } else if imm5&4 == 4 { + a = ArrangementS + index = imm4 >> 2 + } else if imm5&8 == 8 { + a = ArrangementD + index = imm4 >> 3 + } else { + return nil + } + return RegisterWithArrangementAndIndex{V0 + Reg(Rn), a, uint8(index), 0} + + case arg_Vn_arrangement_imm5___B_1__H_2__S_4__D_8_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4__imm5lt4gt_8_1: + var a Arrangement + var index uint32 + Rn := (x >> 5) & (1<<5 - 1) + imm5 := (x >> 16) & (1<<5 - 1) + if imm5&1 == 1 { + a = ArrangementB + index = imm5 >> 1 + } else if imm5&2 == 2 { + a = ArrangementH + index = imm5 >> 2 + } else if imm5&4 == 4 { + a = ArrangementS + index = imm5 >> 3 + } else if imm5&8 == 8 { + a = ArrangementD + index = imm5 >> 4 + } else { + return nil + } + return RegisterWithArrangementAndIndex{V0 + Reg(Rn), a, uint8(index), 0} + + case arg_Vn_arrangement_imm5___B_1__H_2__S_4_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4_1: + var a Arrangement + var index uint32 + Rn := (x >> 5) & (1<<5 - 1) + imm5 := (x >> 16) & (1<<5 - 1) + if imm5&1 == 1 { + a = ArrangementB + index = imm5 >> 1 + } else if imm5&2 == 2 { + a = ArrangementH + index = imm5 >> 2 + } else if imm5&4 == 4 { + a = ArrangementS + index = imm5 >> 3 + } else { + return nil + } + return RegisterWithArrangementAndIndex{V0 + Reg(Rn), a, uint8(index), 0} + + case arg_Vn_arrangement_imm5___D_8_index__imm5_1: + var a Arrangement + var index uint32 + Rn := (x >> 5) & (1<<5 - 1) + imm5 := (x >> 16) & (1<<5 - 1) + if imm5&15 == 8 { + a = ArrangementD + index = imm5 >> 4 + } else { + return nil + } + return RegisterWithArrangementAndIndex{V0 + Reg(Rn), a, uint8(index), 0} + + case arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__2S_40__4S_41__2D_81: + Rn := (x >> 5) & (1<<5 - 1) + immh := (x >> 19) & (1<<4 - 1) + Q := (x >> 30) & 1 + if immh>>2 == 1 { + if Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2S, 0} + } else { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0} + } + } else if immh>>3 == 1 { + if Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2D, 0} + } + } + return nil + + case arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41: + Rn := (x >> 5) & (1<<5 - 1) + immh := (x >> 19) & (1<<4 - 1) + Q := (x >> 30) & 1 + if immh == 1 { + if Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8B, 0} + } else { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 0} + } + } else if immh>>1 == 1 { + if Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4H, 0} + } else { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8H, 0} + } + } else if immh>>2 == 1 { + if Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2S, 0} + } else { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0} + } + } + return nil + + case arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81: + Rn := (x >> 5) & (1<<5 - 1) + immh := (x >> 19) & (1<<4 - 1) + Q := (x >> 30) & 1 + if immh == 1 { + if Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8B, 0} + } else { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 0} + } + } else if immh>>1 == 1 { + if Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4H, 0} + } else { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8H, 0} + } + } else if immh>>2 == 1 { + if Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2S, 0} + } else { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0} + } + } else if immh>>3 == 1 { + if Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2D, 0} + } + } + return nil + + case arg_Vn_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4: + Rn := (x >> 5) & (1<<5 - 1) + immh := (x >> 19) & (1<<4 - 1) + if immh == 1 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8H, 0} + } else if immh>>1 == 1 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0} + } else if immh>>2 == 1 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2D, 0} + } + return nil + + case arg_Vn_arrangement_Q___8B_0__16B_1: + Rn := (x >> 5) & (1<<5 - 1) + Q := (x >> 30) & 1 + if Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8B, 0} + } else { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 0} + } + + case arg_Vn_arrangement_Q_sz___2S_00__4S_10__2D_11: + Rn := (x >> 5) & (1<<5 - 1) + Q := (x >> 30) & 1 + sz := (x >> 22) & 1 + if sz == 0 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2S, 0} + } else if sz == 0 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0} + } else if sz == 1 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2D, 0} + } + return nil + + case arg_Vn_arrangement_Q_sz___4S_10: + Rn := (x >> 5) & (1<<5 - 1) + Q := (x >> 30) & 1 + sz := (x >> 22) & 1 + if sz == 0 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0} + } + return nil + + case arg_Vn_arrangement_S_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4_1: + var index uint32 + Rn := (x >> 5) & (1<<5 - 1) + imm5 := (x >> 16) & (1<<5 - 1) + index = imm5 >> 3 + return RegisterWithArrangementAndIndex{V0 + Reg(Rn), ArrangementS, uint8(index), 0} + + case arg_Vn_arrangement_size___2D_3: + Rn := (x >> 5) & (1<<5 - 1) + size := (x >> 22) & 3 + if size == 3 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2D, 0} + } + return nil + + case arg_Vn_arrangement_size___8H_0__4S_1__2D_2: + Rn := (x >> 5) & (1<<5 - 1) + size := (x >> 22) & 3 + if size == 0 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8H, 0} + } else if size == 1 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0} + } else if size == 2 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2D, 0} + } + return nil + + case arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21: + Rn := (x >> 5) & (1<<5 - 1) + size := (x >> 22) & 3 + Q := (x >> 30) & 1 + if size == 1 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4H, 0} + } else if size == 1 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8H, 0} + } else if size == 2 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2S, 0} + } else if size == 2 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0} + } + return nil + + case arg_Vn_arrangement_size_Q___8B_00__16B_01: + Rn := (x >> 5) & (1<<5 - 1) + size := (x >> 22) & 3 + Q := (x >> 30) & 1 + if size == 0 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8B, 0} + } else if size == 0 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 0} + } + return nil + + case arg_Vn_arrangement_size_Q___8B_00__16B_01__1D_30__2D_31: + Rn := (x >> 5) & (1<<5 - 1) + size := (x >> 22) & 3 + Q := (x >> 30) & 1 + if size == 0 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8B, 0} + } else if size == 0 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 0} + } else if size == 3 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement1D, 0} + } else if size == 3 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2D, 0} + } + return nil + + case arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11: + Rn := (x >> 5) & (1<<5 - 1) + size := (x >> 22) & 3 + Q := (x >> 30) & 1 + if size == 0 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8B, 0} + } else if size == 0 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 0} + } else if size == 1 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4H, 0} + } else if size == 1 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8H, 0} + } + return nil + + case arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21: + Rn := (x >> 5) & (1<<5 - 1) + size := (x >> 22) & 3 + Q := (x >> 30) & 1 + if size == 0 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8B, 0} + } else if size == 0 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 0} + } else if size == 1 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4H, 0} + } else if size == 1 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8H, 0} + } else if size == 2 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2S, 0} + } else if size == 2 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0} + } + return nil + + case arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31: + Rn := (x >> 5) & (1<<5 - 1) + size := (x >> 22) & 3 + Q := (x >> 30) & 1 + if size == 0 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8B, 0} + } else if size == 0 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 0} + } else if size == 1 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4H, 0} + } else if size == 1 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8H, 0} + } else if size == 2 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2S, 0} + } else if size == 2 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0} + } else if size == 3 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2D, 0} + } + return nil + + case arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__4S_21: + Rn := (x >> 5) & (1<<5 - 1) + size := (x >> 22) & 3 + Q := (x >> 30) & 1 + if size == 0 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8B, 0} + } else if size == 0 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 0} + } else if size == 1 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4H, 0} + } else if size == 1 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8H, 0} + } else if size == 2 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0} + } + return nil + + case arg_Vn_arrangement_sz___2D_1: + Rn := (x >> 5) & (1<<5 - 1) + sz := (x >> 22) & 1 + if sz == 1 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2D, 0} + } + return nil + + case arg_Vn_arrangement_sz___2S_0__2D_1: + Rn := (x >> 5) & (1<<5 - 1) + sz := (x >> 22) & 1 + if sz == 0 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2S, 0} + } else { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2D, 0} + } + + case arg_Vn_arrangement_sz___4S_0__2D_1: + Rn := (x >> 5) & (1<<5 - 1) + sz := (x >> 22) & 1 + if sz == 0 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0} + } else { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2D, 0} + } + + case arg_Vn_arrangement_sz_Q___2S_00__4S_01: + Rn := (x >> 5) & (1<<5 - 1) + sz := (x >> 22) & 1 + Q := (x >> 30) & 1 + if sz == 0 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2S, 0} + } else if sz == 0 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0} + } + return nil + + case arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11: + Rn := (x >> 5) & (1<<5 - 1) + sz := (x >> 22) & 1 + Q := (x >> 30) & 1 + if sz == 0 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2S, 0} + } else if sz == 0 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0} + } else if sz == 1 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2D, 0} + } + return nil + + case arg_Vn_arrangement_sz_Q___4H_00__8H_01__2S_10__4S_11: + Rn := (x >> 5) & (1<<5 - 1) + sz := (x >> 22) & 1 + Q := (x >> 30) & 1 + if sz == 0 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4H, 0} + } else if sz == 0 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8H, 0} + } else if sz == 1 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2S, 0} + } else /* sz == 1 && Q == 1 */ { + return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0} + } + + case arg_Vt_1_arrangement_B_index__Q_S_size_1: + Rt := x & (1<<5 - 1) + Q := (x >> 30) & 1 + S := (x >> 12) & 1 + size := (x >> 10) & 3 + index := (Q << 3) | (S << 2) | (size) + return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementB, uint8(index), 1} + + case arg_Vt_1_arrangement_D_index__Q_1: + Rt := x & (1<<5 - 1) + index := (x >> 30) & 1 + return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementD, uint8(index), 1} + + case arg_Vt_1_arrangement_H_index__Q_S_size_1: + Rt := x & (1<<5 - 1) + Q := (x >> 30) & 1 + S := (x >> 12) & 1 + size := (x >> 11) & 1 + index := (Q << 2) | (S << 1) | (size) + return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementH, uint8(index), 1} + + case arg_Vt_1_arrangement_S_index__Q_S_1: + Rt := x & (1<<5 - 1) + Q := (x >> 30) & 1 + S := (x >> 12) & 1 + index := (Q << 1) | S + return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementS, uint8(index), 1} + + case arg_Vt_1_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31: + Rt := x & (1<<5 - 1) + Q := (x >> 30) & 1 + size := (x >> 10) & 3 + if size == 0 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8B, 1} + } else if size == 0 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement16B, 1} + } else if size == 1 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4H, 1} + } else if size == 1 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8H, 1} + } else if size == 2 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2S, 1} + } else if size == 2 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4S, 1} + } else if size == 3 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement1D, 1} + } else /* size == 3 && Q == 1 */ { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2D, 1} + } + + case arg_Vt_2_arrangement_B_index__Q_S_size_1: + Rt := x & (1<<5 - 1) + Q := (x >> 30) & 1 + S := (x >> 12) & 1 + size := (x >> 10) & 3 + index := (Q << 3) | (S << 2) | (size) + return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementB, uint8(index), 2} + + case arg_Vt_2_arrangement_D_index__Q_1: + Rt := x & (1<<5 - 1) + index := (x >> 30) & 1 + return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementD, uint8(index), 2} + + case arg_Vt_2_arrangement_H_index__Q_S_size_1: + Rt := x & (1<<5 - 1) + Q := (x >> 30) & 1 + S := (x >> 12) & 1 + size := (x >> 11) & 1 + index := (Q << 2) | (S << 1) | (size) + return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementH, uint8(index), 2} + + case arg_Vt_2_arrangement_S_index__Q_S_1: + Rt := x & (1<<5 - 1) + Q := (x >> 30) & 1 + S := (x >> 12) & 1 + index := (Q << 1) | S + return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementS, uint8(index), 2} + + case arg_Vt_2_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31: + Rt := x & (1<<5 - 1) + Q := (x >> 30) & 1 + size := (x >> 10) & 3 + if size == 0 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8B, 2} + } else if size == 0 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement16B, 2} + } else if size == 1 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4H, 2} + } else if size == 1 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8H, 2} + } else if size == 2 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2S, 2} + } else if size == 2 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4S, 2} + } else if size == 3 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement1D, 2} + } else /* size == 3 && Q == 1 */ { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2D, 2} + } + + case arg_Vt_2_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31: + Rt := x & (1<<5 - 1) + Q := (x >> 30) & 1 + size := (x >> 10) & 3 + if size == 0 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8B, 2} + } else if size == 0 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement16B, 2} + } else if size == 1 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4H, 2} + } else if size == 1 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8H, 2} + } else if size == 2 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2S, 2} + } else if size == 2 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4S, 2} + } else if size == 3 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2D, 2} + } + return nil + + case arg_Vt_3_arrangement_B_index__Q_S_size_1: + Rt := x & (1<<5 - 1) + Q := (x >> 30) & 1 + S := (x >> 12) & 1 + size := (x >> 10) & 3 + index := (Q << 3) | (S << 2) | (size) + return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementB, uint8(index), 3} + + case arg_Vt_3_arrangement_D_index__Q_1: + Rt := x & (1<<5 - 1) + index := (x >> 30) & 1 + return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementD, uint8(index), 3} + + case arg_Vt_3_arrangement_H_index__Q_S_size_1: + Rt := x & (1<<5 - 1) + Q := (x >> 30) & 1 + S := (x >> 12) & 1 + size := (x >> 11) & 1 + index := (Q << 2) | (S << 1) | (size) + return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementH, uint8(index), 3} + + case arg_Vt_3_arrangement_S_index__Q_S_1: + Rt := x & (1<<5 - 1) + Q := (x >> 30) & 1 + S := (x >> 12) & 1 + index := (Q << 1) | S + return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementS, uint8(index), 3} + + case arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31: + Rt := x & (1<<5 - 1) + Q := (x >> 30) & 1 + size := (x >> 10) & 3 + if size == 0 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8B, 3} + } else if size == 0 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement16B, 3} + } else if size == 1 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4H, 3} + } else if size == 1 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8H, 3} + } else if size == 2 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2S, 3} + } else if size == 2 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4S, 3} + } else if size == 3 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement1D, 3} + } else /* size == 3 && Q == 1 */ { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2D, 3} + } + + case arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31: + Rt := x & (1<<5 - 1) + Q := (x >> 30) & 1 + size := (x >> 10) & 3 + if size == 0 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8B, 3} + } else if size == 0 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement16B, 3} + } else if size == 1 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4H, 3} + } else if size == 1 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8H, 3} + } else if size == 2 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2S, 3} + } else if size == 2 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4S, 3} + } else if size == 3 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2D, 3} + } + return nil + + case arg_Vt_4_arrangement_B_index__Q_S_size_1: + Rt := x & (1<<5 - 1) + Q := (x >> 30) & 1 + S := (x >> 12) & 1 + size := (x >> 10) & 3 + index := (Q << 3) | (S << 2) | (size) + return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementB, uint8(index), 4} + + case arg_Vt_4_arrangement_D_index__Q_1: + Rt := x & (1<<5 - 1) + index := (x >> 30) & 1 + return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementD, uint8(index), 4} + + case arg_Vt_4_arrangement_H_index__Q_S_size_1: + Rt := x & (1<<5 - 1) + Q := (x >> 30) & 1 + S := (x >> 12) & 1 + size := (x >> 11) & 1 + index := (Q << 2) | (S << 1) | (size) + return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementH, uint8(index), 4} + + case arg_Vt_4_arrangement_S_index__Q_S_1: + Rt := x & (1<<5 - 1) + Q := (x >> 30) & 1 + S := (x >> 12) & 1 + index := (Q << 1) | S + return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementS, uint8(index), 4} + + case arg_Vt_4_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31: + Rt := x & (1<<5 - 1) + Q := (x >> 30) & 1 + size := (x >> 10) & 3 + if size == 0 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8B, 4} + } else if size == 0 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement16B, 4} + } else if size == 1 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4H, 4} + } else if size == 1 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8H, 4} + } else if size == 2 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2S, 4} + } else if size == 2 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4S, 4} + } else if size == 3 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement1D, 4} + } else /* size == 3 && Q == 1 */ { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2D, 4} + } + + case arg_Vt_4_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31: + Rt := x & (1<<5 - 1) + Q := (x >> 30) & 1 + size := (x >> 10) & 3 + if size == 0 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8B, 4} + } else if size == 0 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement16B, 4} + } else if size == 1 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4H, 4} + } else if size == 1 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8H, 4} + } else if size == 2 && Q == 0 { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2S, 4} + } else if size == 2 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4S, 4} + } else if size == 3 && Q == 1 { + return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2D, 4} + } + return nil + + case arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__4_1: + return handle_MemExtend(x, 4, false) + + case arg_Xns_mem_offset: + Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1)) + return MemImmediate{Rn, AddrOffset, 0} + + case arg_Xns_mem_optional_imm12_16_unsigned: + Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1)) + imm12 := (x >> 10) & (1<<12 - 1) + return MemImmediate{Rn, AddrOffset, int32(imm12 << 4)} + + case arg_Xns_mem_optional_imm7_16_signed: + Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1)) + imm7 := (x >> 15) & (1<<7 - 1) + return MemImmediate{Rn, AddrOffset, ((int32(imm7 << 4)) << 21) >> 21} + + case arg_Xns_mem_post_fixedimm_1: + Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1)) + return MemImmediate{Rn, AddrPostIndex, 1} + + case arg_Xns_mem_post_fixedimm_12: + Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1)) + return MemImmediate{Rn, AddrPostIndex, 12} + + case arg_Xns_mem_post_fixedimm_16: + Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1)) + return MemImmediate{Rn, AddrPostIndex, 16} + + case arg_Xns_mem_post_fixedimm_2: + Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1)) + return MemImmediate{Rn, AddrPostIndex, 2} + + case arg_Xns_mem_post_fixedimm_24: + Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1)) + return MemImmediate{Rn, AddrPostIndex, 24} + + case arg_Xns_mem_post_fixedimm_3: + Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1)) + return MemImmediate{Rn, AddrPostIndex, 3} + + case arg_Xns_mem_post_fixedimm_32: + Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1)) + return MemImmediate{Rn, AddrPostIndex, 32} + + case arg_Xns_mem_post_fixedimm_4: + Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1)) + return MemImmediate{Rn, AddrPostIndex, 4} + + case arg_Xns_mem_post_fixedimm_6: + Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1)) + return MemImmediate{Rn, AddrPostIndex, 6} + + case arg_Xns_mem_post_fixedimm_8: + Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1)) + return MemImmediate{Rn, AddrPostIndex, 8} + + case arg_Xns_mem_post_imm7_16_signed: + Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1)) + imm7 := (x >> 15) & (1<<7 - 1) + return MemImmediate{Rn, AddrPostIndex, ((int32(imm7 << 4)) << 21) >> 21} + + case arg_Xns_mem_post_Q__16_0__32_1: + Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1)) + Q := (x >> 30) & 1 + return MemImmediate{Rn, AddrPostIndex, int32((Q + 1) * 16)} + + case arg_Xns_mem_post_Q__24_0__48_1: + Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1)) + Q := (x >> 30) & 1 + return MemImmediate{Rn, AddrPostIndex, int32((Q + 1) * 24)} + + case arg_Xns_mem_post_Q__32_0__64_1: + Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1)) + Q := (x >> 30) & 1 + return MemImmediate{Rn, AddrPostIndex, int32((Q + 1) * 32)} + + case arg_Xns_mem_post_Q__8_0__16_1: + Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1)) + Q := (x >> 30) & 1 + return MemImmediate{Rn, AddrPostIndex, int32((Q + 1) * 8)} + + case arg_Xns_mem_post_size__1_0__2_1__4_2__8_3: + Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1)) + size := (x >> 10) & 3 + return MemImmediate{Rn, AddrPostIndex, int32(1 << size)} + + case arg_Xns_mem_post_size__2_0__4_1__8_2__16_3: + Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1)) + size := (x >> 10) & 3 + return MemImmediate{Rn, AddrPostIndex, int32(2 << size)} + + case arg_Xns_mem_post_size__3_0__6_1__12_2__24_3: + Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1)) + size := (x >> 10) & 3 + return MemImmediate{Rn, AddrPostIndex, int32(3 << size)} + + case arg_Xns_mem_post_size__4_0__8_1__16_2__32_3: + Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1)) + size := (x >> 10) & 3 + return MemImmediate{Rn, AddrPostIndex, int32(4 << size)} + + case arg_Xns_mem_post_Xm: + Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1)) + Rm := (x >> 16) & (1<<5 - 1) + return MemImmediate{Rn, AddrPostReg, int32(Rm)} + + case arg_Xns_mem_wb_imm7_16_signed: + Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1)) + imm7 := (x >> 15) & (1<<7 - 1) + return MemImmediate{Rn, AddrPreIndex, ((int32(imm7 << 4)) << 21) >> 21} + } +} + +func handle_ExtendedRegister(x uint32, has_width bool) Arg { + s := (x >> 29) & 1 + rm := (x >> 16) & (1<<5 - 1) + option := (x >> 13) & (1<<3 - 1) + imm3 := (x >> 10) & (1<<3 - 1) + rn := (x >> 5) & (1<<5 - 1) + rd := x & (1<<5 - 1) + is_32bit := !has_width + var rea RegExtshiftAmount + if has_width { + if option&0x3 != 0x3 { + rea.reg = W0 + Reg(rm) + } else { + rea.reg = X0 + Reg(rm) + } + } else { + rea.reg = W0 + Reg(rm) + } + switch option { + case 0: + rea.extShift = uxtb + case 1: + rea.extShift = uxth + case 2: + if is_32bit && (rn == 31 || (s == 0 && rd == 31)) { + if imm3 != 0 { + rea.extShift = lsl + } else { + rea.extShift = ExtShift(0) + } + } else { + rea.extShift = uxtw + } + case 3: + if !is_32bit && (rn == 31 || (s == 0 && rd == 31)) { + if imm3 != 0 { + rea.extShift = lsl + } else { + rea.extShift = ExtShift(0) + } + } else { + rea.extShift = uxtx + } + case 4: + rea.extShift = sxtb + case 5: + rea.extShift = sxth + case 6: + rea.extShift = sxtw + case 7: + rea.extShift = sxtx + } + rea.show_zero = false + rea.amount = uint8(imm3) + return rea +} + +func handle_ImmediateShiftedRegister(x uint32, max uint8, is_w, has_ror bool) Arg { + var rsa RegExtshiftAmount + if is_w { + rsa.reg = W0 + Reg((x>>16)&(1<<5-1)) + } else { + rsa.reg = X0 + Reg((x>>16)&(1<<5-1)) + } + switch (x >> 22) & 0x3 { + case 0: + rsa.extShift = lsl + case 1: + rsa.extShift = lsr + case 2: + rsa.extShift = asr + case 3: + if has_ror { + rsa.extShift = ror + } else { + return nil + } + } + rsa.show_zero = true + rsa.amount = uint8((x >> 10) & (1<<6 - 1)) + if rsa.amount == 0 && rsa.extShift == lsl { + rsa.extShift = ExtShift(0) + } else if rsa.amount > max { + return nil + } + return rsa +} + +func handle_MemExtend(x uint32, mult uint8, absent bool) Arg { + var extend ExtShift + var Rm Reg + option := (x >> 13) & (1<<3 - 1) + Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1)) + if (option & 1) != 0 { + Rm = Reg(X0) + Reg(x>>16&(1<<5-1)) + } else { + Rm = Reg(W0) + Reg(x>>16&(1<<5-1)) + } + switch option { + default: + return nil + case 2: + extend = uxtw + case 3: + extend = lsl + case 6: + extend = sxtw + case 7: + extend = sxtx + } + amount := (uint8((x >> 12) & 1)) * mult + return MemExtend{Rn, Rm, extend, amount, absent} +} + +func handle_bitmasks(x uint32, datasize uint8) Arg { + var length, levels, esize, i uint8 + var welem, wmask uint64 + n := (x >> 22) & 1 + imms := uint8((x >> 10) & (1<<6 - 1)) + immr := uint8((x >> 16) & (1<<6 - 1)) + if n != 0 { + length = 6 + } else if (imms & 32) == 0 { + length = 5 + } else if (imms & 16) == 0 { + length = 4 + } else if (imms & 8) == 0 { + length = 3 + } else if (imms & 4) == 0 { + length = 2 + } else if (imms & 2) == 0 { + length = 1 + } else { + return nil + } + levels = 1< datasize { + return nil + } + welem = 1<<(s+1) - 1 + ror := (welem >> r) | (welem << (esize - r)) + ror &= ((1 << esize) - 1) + wmask = 0 + for i = 0; i < datasize; i += esize { + wmask = (wmask << esize) | ror + } + return Imm64{wmask, false} +} diff --git a/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/decode_test.go b/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/decode_test.go new file mode 100644 index 0000000000..a79ee1cae6 --- /dev/null +++ b/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/decode_test.go @@ -0,0 +1,78 @@ +// Copyright 2017 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package arm64asm + +import ( + "encoding/hex" + "io/ioutil" + "strings" + "testing" +) + +func TestDecode(t *testing.T) { + data, err := ioutil.ReadFile("testdata/cases.txt") + if err != nil { + t.Fatal(err) + } + all := string(data) + for strings.Contains(all, "\t\t") { + all = strings.Replace(all, "\t\t", "\t", -1) + } + for _, line := range strings.Split(all, "\n") { + line = strings.TrimSpace(line) + if line == "" || strings.HasPrefix(line, "#") { + continue + } + f := strings.SplitN(line, "\t", 3) + i := strings.Index(f[0], "|") + if i < 0 { + t.Errorf("parsing %q: missing | separator", f[0]) + continue + } + if i%2 != 0 { + t.Errorf("parsing %q: misaligned | separator", f[0]) + } + code, err := hex.DecodeString(f[0][:i] + f[0][i+1:]) + if err != nil { + t.Errorf("parsing %q: %v", f[0], err) + continue + } + syntax, asm := f[1], f[2] + inst, decodeErr := Decode(code) + if decodeErr != nil && decodeErr != errUnknown { + // Some rarely used system instructions are not supported + // Following logicals will filter such unknown instructions + + t.Errorf("parsing %x: %s", code, decodeErr) + continue + } + var out string + switch syntax { + case "gnu": + out = GNUSyntax(inst) + case "plan9": + out = GoSyntax(inst, 0, nil, nil) + default: + t.Errorf("unknown syntax %q", syntax) + continue + } + // TODO: system instruction. + var Todo = strings.Fields(` + sys + dc + at + tlbi + ic + hvc + smc + `) + if strings.Replace(out, " ", "", -1) != strings.Replace(asm, " ", "", -1) && !hasPrefix(asm, Todo...) { + // Exclude MSR since GNU objdump result is incorrect. eg. 0xd504431f msr s0_4_c4_c3_0, xzr + if !strings.HasSuffix(asm, " nv") && !strings.HasPrefix(asm, "msr") { + t.Errorf("Decode(%s) [%s] = %s, want %s", f[0], syntax, out, asm) + } + } + } +} diff --git a/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/ext_test.go b/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/ext_test.go new file mode 100644 index 0000000000..ef2162cf77 --- /dev/null +++ b/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/ext_test.go @@ -0,0 +1,601 @@ +// Copyright 2017 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +// Support for testing against external disassembler program. +// Copied and simplified from ../../arm/armasm/ext_test.go. + +package arm64asm + +import ( + "bufio" + "bytes" + "encoding/hex" + "encoding/json" + "flag" + "fmt" + "io/ioutil" + "log" + "math/rand" + "os" + "os/exec" + "regexp" + "strconv" + "strings" + "testing" + "time" +) + +var ( + dumpTest = flag.Bool("dump", false, "dump all encodings") + mismatch = flag.Bool("mismatch", false, "log allowed mismatches") + longTest = flag.Bool("long", false, "long test") + keep = flag.Bool("keep", false, "keep object files around") + debug = false +) + +// An ExtInst represents a single decoded instruction parsed +// from an external disassembler's output. +type ExtInst struct { + addr uint64 + enc [4]byte + nenc int + text string +} + +func (r ExtInst) String() string { + return fmt.Sprintf("%#x: % x: %s", r.addr, r.enc, r.text) +} + +// An ExtDis is a connection between an external disassembler and a test. +type ExtDis struct { + Arch Mode + Dec chan ExtInst + File *os.File + Size int + KeepFile bool + Cmd *exec.Cmd +} + +// InstJson describes instruction fields value got from ARMv8-A Reference Manual +type InstJson struct { + Name string + Bits string + Arch string + Syntax string + Code string + Alias string + Enc uint32 +} + +// A Mode is an instruction execution mode. +type Mode int + +const ( + _ Mode = iota + ModeARM64 +) + +// Run runs the given command - the external disassembler - and returns +// a buffered reader of its standard output. +func (ext *ExtDis) Run(cmd ...string) (*bufio.Reader, error) { + if *keep { + log.Printf("%s\n", strings.Join(cmd, " ")) + } + ext.Cmd = exec.Command(cmd[0], cmd[1:]...) + out, err := ext.Cmd.StdoutPipe() + if err != nil { + return nil, fmt.Errorf("stdoutpipe: %v", err) + } + if err := ext.Cmd.Start(); err != nil { + return nil, fmt.Errorf("exec: %v", err) + } + + b := bufio.NewReaderSize(out, 1<<20) + return b, nil +} + +// Wait waits for the command started with Run to exit. +func (ext *ExtDis) Wait() error { + return ext.Cmd.Wait() +} + +// testExtDis tests a set of byte sequences against an external disassembler. +// The disassembler is expected to produce the given syntax and run +// in the given architecture mode (16, 32, or 64-bit). +// The extdis function must start the external disassembler +// and then parse its output, sending the parsed instructions on ext.Dec. +// The generate function calls its argument f once for each byte sequence +// to be tested. The generate function itself will be called twice, and it must +// make the same sequence of calls to f each time. +// When a disassembly does not match the internal decoding, +// allowedMismatch determines whether this mismatch should be +// allowed, or else considered an error. +func testExtDis( + t *testing.T, + syntax string, + arch Mode, + extdis func(ext *ExtDis) error, + generate func(f func([]byte)), + allowedMismatch func(text string, inst *Inst, dec ExtInst) bool, +) { + start := time.Now() + ext := &ExtDis{ + Dec: make(chan ExtInst), + Arch: arch, + } + errc := make(chan error) + + // First pass: write instructions to input file for external disassembler. + file, f, size, err := writeInst(generate) + if err != nil { + t.Fatal(err) + } + ext.Size = size + ext.File = f + defer func() { + f.Close() + if !*keep { + os.Remove(file) + } + }() + + // Second pass: compare disassembly against our decodings. + var ( + totalTests = 0 + totalSkips = 0 + totalErrors = 0 + + errors = make([]string, 0, 100) // Sampled errors, at most cap + ) + go func() { + errc <- extdis(ext) + }() + + generate(func(enc []byte) { + dec, ok := <-ext.Dec + if !ok { + t.Errorf("decoding stream ended early") + return + } + inst, text := disasm(syntax, pad(enc)) + + totalTests++ + if *dumpTest { + fmt.Printf("%x -> %s [%d]\n", enc[:len(enc)], dec.text, dec.nenc) + } + if text != dec.text && !strings.Contains(dec.text, "unknown") && syntax == "gnu" { + suffix := "" + if allowedMismatch(text, &inst, dec) { + totalSkips++ + if !*mismatch { + return + } + suffix += " (allowed mismatch)" + } + totalErrors++ + cmp := fmt.Sprintf("decode(%x) = %q, %d, want %q, %d%s\n", enc, text, len(enc), dec.text, dec.nenc, suffix) + + if len(errors) >= cap(errors) { + j := rand.Intn(totalErrors) + if j >= cap(errors) { + return + } + errors = append(errors[:j], errors[j+1:]...) + } + errors = append(errors, cmp) + } + }) + + if *mismatch { + totalErrors -= totalSkips + } + + for _, b := range errors { + t.Log(b) + } + + if totalErrors > 0 { + t.Fail() + } + t.Logf("%d test cases, %d expected mismatches, %d failures; %.0f cases/second", totalTests, totalSkips, totalErrors, float64(totalTests)/time.Since(start).Seconds()) + t.Logf("decoder coverage: %.1f%%;\n", decodeCoverage()) + if err := <-errc; err != nil { + t.Fatalf("external disassembler: %v", err) + } + +} + +// Start address of text. +const start = 0x8000 + +// writeInst writes the generated byte sequences to a new file +// starting at offset start. That file is intended to be the input to +// the external disassembler. +func writeInst(generate func(func([]byte))) (file string, f *os.File, size int, err error) { + f, err = ioutil.TempFile("", "arm64asm") + if err != nil { + return + } + + file = f.Name() + + f.Seek(start, 0) + w := bufio.NewWriter(f) + defer w.Flush() + size = 0 + generate(func(x []byte) { + if debug { + fmt.Printf("%#x: %x%x\n", start+size, x, zeros[len(x):]) + } + w.Write(x) + w.Write(zeros[len(x):]) + size += len(zeros) + }) + return file, f, size, nil +} + +var zeros = []byte{0, 0, 0, 0} + +// pad pads the code sequence with pops. +func pad(enc []byte) []byte { + if len(enc) < 4 { + enc = append(enc[:len(enc):len(enc)], zeros[:4-len(enc)]...) + } + return enc +} + +// disasm returns the decoded instruction and text +// for the given source bytes, using the given syntax and mode. +func disasm(syntax string, src []byte) (inst Inst, text string) { + var err error + inst, err = Decode(src) + if err != nil { + text = "error: " + err.Error() + return + } + text = inst.String() + switch syntax { + case "gnu": + text = GNUSyntax(inst) + case "plan9": // [sic] + text = GoSyntax(inst, 0, nil, nil) + default: + text = "error: unknown syntax " + syntax + } + return +} + +// decodecoverage returns a floating point number denoting the +// decoder coverage. +func decodeCoverage() float64 { + n := 0 + for _, t := range decoderCover { + if t { + n++ + } + } + return 100 * float64(1+n) / float64(1+len(decoderCover)) +} + +// Helpers for writing disassembler output parsers. + +// hasPrefix reports whether any of the space-separated words in the text s +// begins with any of the given prefixes. +func hasPrefix(s string, prefixes ...string) bool { + for _, prefix := range prefixes { + for cur_s := s; cur_s != ""; { + if strings.HasPrefix(cur_s, prefix) { + return true + } + i := strings.Index(cur_s, " ") + if i < 0 { + break + } + cur_s = cur_s[i+1:] + } + } + return false +} + +// isHex reports whether b is a hexadecimal character (0-9a-fA-F). +func isHex(b byte) bool { + return ('0' <= b && b <= '9') || ('a' <= b && b <= 'f') || ('A' <= b && b <= 'F') +} + +// parseHex parses the hexadecimal byte dump in hex, +// appending the parsed bytes to raw and returning the updated slice. +// The returned bool reports whether any invalid hex was found. +// Spaces and tabs between bytes are okay but any other non-hex is not. +func parseHex(hex []byte, raw []byte) ([]byte, bool) { + hex = bytes.TrimSpace(hex) + for j := 0; j < len(hex); { + for hex[j] == ' ' || hex[j] == '\t' { + j++ + } + if j >= len(hex) { + break + } + if j+2 > len(hex) || !isHex(hex[j]) || !isHex(hex[j+1]) { + return nil, false + } + raw = append(raw, unhex(hex[j])<<4|unhex(hex[j+1])) + j += 2 + } + return raw, true +} + +func unhex(b byte) byte { + if '0' <= b && b <= '9' { + return b - '0' + } else if 'A' <= b && b <= 'F' { + return b - 'A' + 10 + } else if 'a' <= b && b <= 'f' { + return b - 'a' + 10 + } + return 0 +} + +// index is like bytes.Index(s, []byte(t)) but avoids the allocation. +func index(s []byte, t string) int { + i := 0 + for { + j := bytes.IndexByte(s[i:], t[0]) + if j < 0 { + return -1 + } + i = i + j + if i+len(t) > len(s) { + return -1 + } + for k := 1; k < len(t); k++ { + if s[i+k] != t[k] { + goto nomatch + } + } + return i + nomatch: + i++ + } +} + +// fixSpace rewrites runs of spaces, tabs, and newline characters into single spaces in s. +// If s must be rewritten, it is rewritten in place. +func fixSpace(s []byte) []byte { + s = bytes.TrimSpace(s) + for i := 0; i < len(s); i++ { + if s[i] == '\t' || s[i] == '\n' || i > 0 && s[i] == ' ' && s[i-1] == ' ' { + goto Fix + } + } + return s + +Fix: + b := s + w := 0 + for i := 0; i < len(s); i++ { + c := s[i] + if c == '\t' || c == '\n' { + c = ' ' + } + if c == ' ' && w > 0 && b[w-1] == ' ' { + continue + } + b[w] = c + w++ + } + if w > 0 && b[w-1] == ' ' { + w-- + } + return b[:w] +} + +// Fllowing regular expressions matches instructions using relative addressing mode. +// pcrel matches B instructions and BL instructions. +// pcrelr matches instrucions which consisted of register arguments and label arguments. +// pcrelim matches instructions which consisted of register arguments, immediate +// arguments and lable arguments. +// pcrelrzr and prcelimzr matches instructions when register arguments is zero register. +// pcrelprfm matches PRFM instructions when arguments consisted of register and lable. +// pcrelprfmim matches PRFM instructions when arguments consisted of immediate and lable. +var ( + pcrel = regexp.MustCompile(`^((?:.* )?(?:b|bl)x?(?:\.)?(?:eq|ne|cs|cc|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv)?) 0x([0-9a-f]+)$`) + pcrelr = regexp.MustCompile(`^((?:.*)?(?:ldr|adrp|adr|cbnz|cbz|ldrsw) (?:x|w|s|d|q)(?:[0-9]+,)) 0x([0-9a-f]+)$`) + pcrelrzr = regexp.MustCompile(`^((?:.*)?(?:ldr|adrp|adr|cbnz|cbz|ldrsw) (?:x|w)zr,) 0x([0-9a-f]+)$`) + pcrelim = regexp.MustCompile(`^((?:.*)?(?:tbnz|tbz) (?:x|w)(?:[0-9]+,) (?:#[0-9a-f]+,)) 0x([0-9a-f]+)$`) + pcrelimzr = regexp.MustCompile(`^((?:.*)?(?:tbnz|tbz) (?:x|w)zr, (?:#[0-9a-f]+,)) 0x([0-9a-f]+)$`) + pcrelprfm = regexp.MustCompile(`^((?:.*)?(?:prfm) (?:[0-9a-z]+,)) 0x([0-9a-f]+)$`) + pcrelprfmim = regexp.MustCompile(`^((?:.*)?(?:prfm) (?:#0x[0-9a-f]+,)) 0x([0-9a-f]+)$`) +) + +// Round is the multiple of the number of instructions that read from Json file. +// Round used as seed value for pseudo-random number generator provides the same sequence +// in the same round run for the external disassembler and decoder. +var Round int + +// condmark is used to mark conditional instructions when need to generate and test +// conditional instructions. +var condmark bool = false + +// Generate instruction binary according to Json file +// Encode variable field of instruction with random value +func doFuzzy(inst *InstJson, Ninst int) { + var testdata uint32 + var NonDigRE = regexp.MustCompile(`[\D]`) + rand.Seed(int64(Round + Ninst)) + off := 0 + DigBit := "" + if condmark == true && !strings.Contains(inst.Bits, "cond") { + inst.Enc = 0xffffffff + } else { + for _, f := range strings.Split(inst.Bits, "|") { + if i := strings.Index(f, ":"); i >= 0 { + // consider f contains "01:2" and "Rm:5" + DigBit = f[:i] + m := NonDigRE.FindStringSubmatch(DigBit) + if m == nil { + DigBit = strings.TrimSpace(DigBit) + s := strings.Split(DigBit, "") + for i := 0; i < len(s); i++ { + switch s[i] { + case "1", "(1)": + testdata |= 1 << uint(31-off) + } + off++ + } + } else { + // DigBit is "Rn" or "imm3" + n, _ := strconv.Atoi(f[i+1:]) + if DigBit == "cond" && condmark == true { + r := uint8(Round) + for i := n - 1; i >= 0; i-- { + switch (r >> uint(i)) & 1 { + case 1: + testdata |= 1 << uint(31-off) + } + off++ + } + } else { + for i := 0; i < n; i++ { + r := rand.Intn(2) + switch r { + case 1: + testdata |= 1 << uint(31-off) + } + off++ + } + } + } + continue + } + for _, bit := range strings.Fields(f) { + switch bit { + case "0", "(0)": + off++ + continue + case "1", "(1)": + testdata |= 1 << uint(31-off) + default: + r := rand.Intn(2) + switch r { + case 1: + testdata |= 1 << uint(31-off) + } + } + off++ + } + } + if off != 32 { + log.Printf("incorrect bit count for %s %s: have %d", inst.Name, inst.Bits, off) + } + inst.Enc = testdata + } +} + +// Generators. +// +// The test cases are described as functions that invoke a callback repeatedly, +// with a new input sequence each time. These helpers make writing those +// a little easier. + +// JSONCases generates ARM64 instructions according to inst.json. +func JSONCases(t *testing.T) func(func([]byte)) { + return func(try func([]byte)) { + data, err := ioutil.ReadFile("inst.json") + if err != nil { + log.Fatal(err) + } + var insts []InstJson + var instsN []InstJson + // Change N value to get more cases only when condmark=false. + N := 100 + if condmark == true { + N = 16 + } + if err := json.Unmarshal(data, &insts); err != nil { + log.Fatal(err) + } + // Append instructions to get more test cases. + for i := 0; i < N; { + for _, inst := range insts { + instsN = append(instsN, inst) + } + i++ + } + Round = 0 + for i := range instsN { + if i%len(insts) == 0 { + Round++ + } + doFuzzy(&instsN[i], i) + } + for _, inst := range instsN { + if condmark == true && inst.Enc == 0xffffffff { + continue + } + enc := inst.Enc + try([]byte{byte(enc), byte(enc >> 8), byte(enc >> 16), byte(enc >> 24)}) + } + } +} + +// condCases generates conditional instructions. +func condCases(t *testing.T) func(func([]byte)) { + return func(try func([]byte)) { + condmark = true + JSONCases(t)(func(enc []byte) { + try(enc) + }) + } +} + +// hexCases generates the cases written in hexadecimal in the encoded string. +// Spaces in 'encoded' separate entire test cases, not individual bytes. +func hexCases(t *testing.T, encoded string) func(func([]byte)) { + return func(try func([]byte)) { + for _, x := range strings.Fields(encoded) { + src, err := hex.DecodeString(x) + if err != nil { + t.Errorf("parsing %q: %v", x, err) + } + try(src) + } + } +} + +// testdataCases generates the test cases recorded in testdata/cases.txt. +// It only uses the inputs; it ignores the answers recorded in that file. +func testdataCases(t *testing.T) func(func([]byte)) { + var codes [][]byte + data, err := ioutil.ReadFile("testdata/cases.txt") + if err != nil { + t.Fatal(err) + } + for _, line := range strings.Split(string(data), "\n") { + line = strings.TrimSpace(line) + if line == "" || strings.HasPrefix(line, "#") { + continue + } + f := strings.Fields(line)[0] + i := strings.Index(f, "|") + if i < 0 { + t.Errorf("parsing %q: missing | separator", f) + continue + } + if i%2 != 0 { + t.Errorf("parsing %q: misaligned | separator", f) + } + code, err := hex.DecodeString(f[:i] + f[i+1:]) + if err != nil { + t.Errorf("parsing %q: %v", f, err) + continue + } + codes = append(codes, code) + } + + return func(try func([]byte)) { + for _, code := range codes { + try(code) + } + } +} diff --git a/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/gnu.go b/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/gnu.go new file mode 100644 index 0000000000..d1be046173 --- /dev/null +++ b/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/gnu.go @@ -0,0 +1,35 @@ +// Copyright 2017 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package arm64asm + +import ( + "strings" +) + +// GNUSyntax returns the GNU assembler syntax for the instruction, as defined by GNU binutils. +// This form typically matches the syntax defined in the ARM Reference Manual. +func GNUSyntax(inst Inst) string { + switch inst.Op { + case RET: + if r, ok := inst.Args[0].(Reg); ok && r == X30 { + return "ret" + } + case B: + if _, ok := inst.Args[0].(Cond); ok { + return strings.ToLower("b." + inst.Args[0].String() + " " + inst.Args[1].String()) + } + case SYSL: + result := strings.ToLower(inst.String()) + return strings.Replace(result, "c", "C", -1) + case DCPS1, DCPS2, DCPS3, CLREX: + return strings.ToLower(strings.TrimSpace(inst.String())) + case ISB: + if strings.Contains(inst.String(), "SY") { + result := strings.TrimSuffix(inst.String(), " SY") + return strings.ToLower(result) + } + } + return strings.ToLower(inst.String()) +} diff --git a/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/inst.go b/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/inst.go new file mode 100644 index 0000000000..3ff31be222 --- /dev/null +++ b/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/inst.go @@ -0,0 +1,963 @@ +// Copyright 2017 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package arm64asm + +import ( + "fmt" + "strings" +) + +// An Op is an ARM64 opcode. +type Op uint16 + +// NOTE: The actual Op values are defined in tables.go. +// They are chosen to simplify instruction decoding and +// are not a dense packing from 0 to N, although the +// density is high, probably at least 90%. + +func (op Op) String() string { + if op >= Op(len(opstr)) || opstr[op] == "" { + return fmt.Sprintf("Op(%d)", int(op)) + } + return opstr[op] +} + +// An Inst is a single instruction. +type Inst struct { + Op Op // Opcode mnemonic + Enc uint32 // Raw encoding bits. + Args Args // Instruction arguments, in ARM manual order. +} + +func (i Inst) String() string { + var args []string + for _, arg := range i.Args { + if arg == nil { + break + } + args = append(args, arg.String()) + } + return i.Op.String() + " " + strings.Join(args, ", ") +} + +// An Args holds the instruction arguments. +// If an instruction has fewer than 5 arguments, +// the final elements in the array are nil. +type Args [5]Arg + +// An Arg is a single instruction argument, one of these types: +// Reg, RegSP, ImmShift, RegExtshiftAmount, PCRel, MemImmediate, +// MemExtend, Imm, Imm64, Imm_hint, Imm_clrex, Imm_dcps, Cond, +// Imm_c, Imm_option, Imm_prfop, Pstatefield, Systemreg, Imm_fp +// RegisterWithArrangement, RegisterWithArrangementAndIndex. +type Arg interface { + isArg() + String() string +} + +// A Reg is a single register. +// The zero value denotes W0, not the absence of a register. +type Reg uint16 + +const ( + W0 Reg = iota + W1 + W2 + W3 + W4 + W5 + W6 + W7 + W8 + W9 + W10 + W11 + W12 + W13 + W14 + W15 + W16 + W17 + W18 + W19 + W20 + W21 + W22 + W23 + W24 + W25 + W26 + W27 + W28 + W29 + W30 + WZR + + X0 + X1 + X2 + X3 + X4 + X5 + X6 + X7 + X8 + X9 + X10 + X11 + X12 + X13 + X14 + X15 + X16 + X17 + X18 + X19 + X20 + X21 + X22 + X23 + X24 + X25 + X26 + X27 + X28 + X29 + X30 + XZR + + B0 + B1 + B2 + B3 + B4 + B5 + B6 + B7 + B8 + B9 + B10 + B11 + B12 + B13 + B14 + B15 + B16 + B17 + B18 + B19 + B20 + B21 + B22 + B23 + B24 + B25 + B26 + B27 + B28 + B29 + B30 + B31 + + H0 + H1 + H2 + H3 + H4 + H5 + H6 + H7 + H8 + H9 + H10 + H11 + H12 + H13 + H14 + H15 + H16 + H17 + H18 + H19 + H20 + H21 + H22 + H23 + H24 + H25 + H26 + H27 + H28 + H29 + H30 + H31 + + S0 + S1 + S2 + S3 + S4 + S5 + S6 + S7 + S8 + S9 + S10 + S11 + S12 + S13 + S14 + S15 + S16 + S17 + S18 + S19 + S20 + S21 + S22 + S23 + S24 + S25 + S26 + S27 + S28 + S29 + S30 + S31 + + D0 + D1 + D2 + D3 + D4 + D5 + D6 + D7 + D8 + D9 + D10 + D11 + D12 + D13 + D14 + D15 + D16 + D17 + D18 + D19 + D20 + D21 + D22 + D23 + D24 + D25 + D26 + D27 + D28 + D29 + D30 + D31 + + Q0 + Q1 + Q2 + Q3 + Q4 + Q5 + Q6 + Q7 + Q8 + Q9 + Q10 + Q11 + Q12 + Q13 + Q14 + Q15 + Q16 + Q17 + Q18 + Q19 + Q20 + Q21 + Q22 + Q23 + Q24 + Q25 + Q26 + Q27 + Q28 + Q29 + Q30 + Q31 + + V0 + V1 + V2 + V3 + V4 + V5 + V6 + V7 + V8 + V9 + V10 + V11 + V12 + V13 + V14 + V15 + V16 + V17 + V18 + V19 + V20 + V21 + V22 + V23 + V24 + V25 + V26 + V27 + V28 + V29 + V30 + V31 + + WSP = WZR // These are different registers with the same encoding. + SP = XZR // These are different registers with the same encoding. +) + +func (Reg) isArg() {} + +func (r Reg) String() string { + switch { + case r == WZR: + return "WZR" + case r == XZR: + return "XZR" + case W0 <= r && r <= W30: + return fmt.Sprintf("W%d", int(r-W0)) + case X0 <= r && r <= X30: + return fmt.Sprintf("X%d", int(r-X0)) + + case B0 <= r && r <= B31: + return fmt.Sprintf("B%d", int(r-B0)) + case H0 <= r && r <= H31: + return fmt.Sprintf("H%d", int(r-H0)) + case S0 <= r && r <= S31: + return fmt.Sprintf("S%d", int(r-S0)) + case D0 <= r && r <= D31: + return fmt.Sprintf("D%d", int(r-D0)) + case Q0 <= r && r <= Q31: + return fmt.Sprintf("Q%d", int(r-Q0)) + + case V0 <= r && r <= V31: + return fmt.Sprintf("V%d", int(r-V0)) + default: + return fmt.Sprintf("Reg(%d)", int(r)) + } +} + +// A RegSP represent a register and X31/W31 is regarded as SP/WSP. +type RegSP Reg + +func (RegSP) isArg() {} + +func (r RegSP) String() string { + switch Reg(r) { + case WSP: + return "WSP" + case SP: + return "SP" + default: + return Reg(r).String() + } +} + +type ImmShift struct { + imm uint16 + shift uint8 +} + +func (ImmShift) isArg() {} + +func (is ImmShift) String() string { + if is.shift == 0 { + return fmt.Sprintf("#%#x", is.imm) + } + if is.shift < 128 { + return fmt.Sprintf("#%#x, LSL #%d", is.imm, is.shift) + } + return fmt.Sprintf("#%#x, MSL #%d", is.imm, is.shift-128) +} + +type ExtShift uint8 + +const ( + _ ExtShift = iota + uxtb + uxth + uxtw + uxtx + sxtb + sxth + sxtw + sxtx + lsl + lsr + asr + ror +) + +func (extShift ExtShift) String() string { + switch extShift { + case uxtb: + return "UXTB" + + case uxth: + return "UXTH" + + case uxtw: + return "UXTW" + + case uxtx: + return "UXTX" + + case sxtb: + return "SXTB" + + case sxth: + return "SXTH" + + case sxtw: + return "SXTW" + + case sxtx: + return "SXTX" + + case lsl: + return "LSL" + + case lsr: + return "LSR" + + case asr: + return "ASR" + + case ror: + return "ROR" + } + return "" +} + +type RegExtshiftAmount struct { + reg Reg + extShift ExtShift + amount uint8 + show_zero bool +} + +func (RegExtshiftAmount) isArg() {} + +func (rea RegExtshiftAmount) String() string { + buf := rea.reg.String() + if rea.extShift != ExtShift(0) { + buf += ", " + rea.extShift.String() + if rea.amount != 0 { + buf += fmt.Sprintf(" #%d", rea.amount) + } else { + if rea.show_zero == true { + buf += fmt.Sprintf(" #%d", rea.amount) + } + } + } + return buf +} + +// A PCRel describes a memory address (usually a code label) +// as a distance relative to the program counter. +type PCRel int64 + +func (PCRel) isArg() {} + +func (r PCRel) String() string { + return fmt.Sprintf(".%+#x", uint64(r)) +} + +// An AddrMode is an ARM addressing mode. +type AddrMode uint8 + +const ( + _ AddrMode = iota + AddrPostIndex // [R], X - use address R, set R = R + X + AddrPreIndex // [R, X]! - use address R + X, set R = R + X + AddrOffset // [R, X] - use address R + X + AddrPostReg // [Rn], Rm - - use address Rn, set Rn = Rn + Rm +) + +// A MemImmediate is a memory reference made up of a base R and immediate X. +// The effective memory address is R or R+X depending on AddrMode. +type MemImmediate struct { + Base RegSP + Mode AddrMode + imm int32 +} + +func (MemImmediate) isArg() {} + +func (m MemImmediate) String() string { + R := m.Base.String() + X := fmt.Sprintf("#%d", m.imm) + + switch m.Mode { + case AddrOffset: + if X == "#0" { + return fmt.Sprintf("[%s]", R) + } + return fmt.Sprintf("[%s,%s]", R, X) + case AddrPreIndex: + return fmt.Sprintf("[%s,%s]!", R, X) + case AddrPostIndex: + return fmt.Sprintf("[%s],%s", R, X) + case AddrPostReg: + post := Reg(X0) + Reg(m.imm) + postR := post.String() + return fmt.Sprintf("[%s], %s", R, postR) + } + return fmt.Sprintf("unimplemented!") +} + +// A MemExtend is a memory reference made up of a base R and index expression X. +// The effective memory address is R or R+X depending on Index, Extend and Amount. +type MemExtend struct { + Base RegSP + Index Reg + Extend ExtShift + Amount uint8 + Absent bool +} + +func (MemExtend) isArg() {} + +func (m MemExtend) String() string { + Rbase := m.Base.String() + RIndex := m.Index.String() + if m.Absent { + if m.Amount != 0 { + return fmt.Sprintf("[%s,%s,%s #0]", Rbase, RIndex, m.Extend.String()) + } else { + if m.Extend != lsl { + return fmt.Sprintf("[%s,%s,%s]", Rbase, RIndex, m.Extend.String()) + } else { + return fmt.Sprintf("[%s,%s]", Rbase, RIndex) + } + } + } else { + if m.Amount != 0 { + return fmt.Sprintf("[%s,%s,%s #%d]", Rbase, RIndex, m.Extend.String(), m.Amount) + } else { + if m.Extend != lsl { + return fmt.Sprintf("[%s,%s,%s]", Rbase, RIndex, m.Extend.String()) + } else { + return fmt.Sprintf("[%s,%s]", Rbase, RIndex) + } + } + } +} + +// An Imm is an integer constant. +type Imm struct { + Imm uint32 + Decimal bool +} + +func (Imm) isArg() {} + +func (i Imm) String() string { + if !i.Decimal { + return fmt.Sprintf("#%#x", i.Imm) + } else { + return fmt.Sprintf("#%d", i.Imm) + } +} + +type Imm64 struct { + Imm uint64 + Decimal bool +} + +func (Imm64) isArg() {} + +func (i Imm64) String() string { + if !i.Decimal { + return fmt.Sprintf("#%#x", i.Imm) + } else { + return fmt.Sprintf("#%d", i.Imm) + } +} + +// An Imm_hint is an integer constant for HINT instruction. +type Imm_hint uint8 + +func (Imm_hint) isArg() {} + +func (i Imm_hint) String() string { + return fmt.Sprintf("#%#x", uint32(i)) +} + +// An Imm_clrex is an integer constant for CLREX instruction. +type Imm_clrex uint8 + +func (Imm_clrex) isArg() {} + +func (i Imm_clrex) String() string { + if i == 15 { + return "" + } + return fmt.Sprintf("#%#x", uint32(i)) +} + +// An Imm_dcps is an integer constant for DCPS[123] instruction. +type Imm_dcps uint16 + +func (Imm_dcps) isArg() {} + +func (i Imm_dcps) String() string { + if i == 0 { + return "" + } + return fmt.Sprintf("#%#x", uint32(i)) +} + +// Standard conditions. +type Cond struct { + Value uint8 + Invert bool +} + +func (Cond) isArg() {} + +func (c Cond) String() string { + cond31 := c.Value >> 1 + invert := bool((c.Value & 1) == 1) + invert = (invert != c.Invert) + switch cond31 { + case 0: + if invert { + return "NE" + } else { + return "EQ" + } + case 1: + if invert { + return "CC" + } else { + return "CS" + } + case 2: + if invert { + return "PL" + } else { + return "MI" + } + case 3: + if invert { + return "VC" + } else { + return "VS" + } + case 4: + if invert { + return "LS" + } else { + return "HI" + } + case 5: + if invert { + return "LT" + } else { + return "GE" + } + case 6: + if invert { + return "LE" + } else { + return "GT" + } + case 7: + return "AL" + } + return "" +} + +// An Imm_c is an integer constant for SYS/SYSL/TLBI instruction. +type Imm_c uint8 + +func (Imm_c) isArg() {} + +func (i Imm_c) String() string { + return fmt.Sprintf("C%d", uint8(i)) +} + +// An Imm_option is an integer constant for DMB/DSB/ISB instruction. +type Imm_option uint8 + +func (Imm_option) isArg() {} + +func (i Imm_option) String() string { + switch uint8(i) { + case 15: + return "SY" + case 14: + return "ST" + case 13: + return "LD" + case 11: + return "ISH" + case 10: + return "ISHST" + case 9: + return "ISHLD" + case 7: + return "NSH" + case 6: + return "NSHST" + case 5: + return "NSHLD" + case 3: + return "OSH" + case 2: + return "OSHST" + case 1: + return "OSHLD" + } + return fmt.Sprintf("#%#02x", uint8(i)) +} + +// An Imm_prfop is an integer constant for PRFM instruction. +type Imm_prfop uint8 + +func (Imm_prfop) isArg() {} + +func (i Imm_prfop) String() string { + prf_type := (i >> 3) & (1<<2 - 1) + prf_target := (i >> 1) & (1<<2 - 1) + prf_policy := i & 1 + var result string + + switch prf_type { + case 0: + result = "PLD" + case 1: + result = "PLI" + case 2: + result = "PST" + case 3: + return fmt.Sprintf("#%#02x", uint8(i)) + } + switch prf_target { + case 0: + result += "L1" + case 1: + result += "L2" + case 2: + result += "L3" + case 3: + return fmt.Sprintf("#%#02x", uint8(i)) + } + if prf_policy == 0 { + result += "KEEP" + } else { + result += "STRM" + } + return result +} + +type Pstatefield uint8 + +const ( + SPSel Pstatefield = iota + DAIFSet + DAIFClr +) + +func (Pstatefield) isArg() {} + +func (p Pstatefield) String() string { + switch p { + case SPSel: + return "SPSel" + case DAIFSet: + return "DAIFSet" + case DAIFClr: + return "DAIFClr" + default: + return "unimplemented" + } +} + +type Systemreg struct { + op0 uint8 + op1 uint8 + cn uint8 + cm uint8 + op2 uint8 +} + +func (Systemreg) isArg() {} + +func (s Systemreg) String() string { + return fmt.Sprintf("S%d_%d_C%d_C%d_%d", + s.op0, s.op1, s.cn, s.cm, s.op2) +} + +// An Imm_fp is a signed floating-point constant. +type Imm_fp struct { + s uint8 + exp int8 + pre uint8 +} + +func (Imm_fp) isArg() {} + +func (i Imm_fp) String() string { + var s, pre, numerator, denominator int16 + var result float64 + if i.s == 0 { + s = 1 + } else { + s = -1 + } + pre = s * int16(16+i.pre) + if i.exp > 0 { + numerator = (pre << uint8(i.exp)) + denominator = 16 + } else { + numerator = pre + denominator = (16 << uint8(-1*i.exp)) + } + result = float64(numerator) / float64(denominator) + return fmt.Sprintf("#%.18e", result) +} + +type Arrangement uint8 + +const ( + _ Arrangement = iota + ArrangementB + Arrangement8B + Arrangement16B + ArrangementH + Arrangement4H + Arrangement8H + ArrangementS + Arrangement2S + Arrangement4S + ArrangementD + Arrangement1D + Arrangement2D + Arrangement1Q +) + +func (a Arrangement) String() (result string) { + switch a { + case ArrangementB: + result = ".B" + case Arrangement8B: + result = ".8B" + case Arrangement16B: + result = ".16B" + case ArrangementH: + result = ".H" + case Arrangement4H: + result = ".4H" + case Arrangement8H: + result = ".8H" + case ArrangementS: + result = ".S" + case Arrangement2S: + result = ".2S" + case Arrangement4S: + result = ".4S" + case ArrangementD: + result = ".D" + case Arrangement1D: + result = ".1D" + case Arrangement2D: + result = ".2D" + case Arrangement1Q: + result = ".1Q" + } + return +} + +// Register with arrangement: ., { .8B, .8B}, +type RegisterWithArrangement struct { + r Reg + a Arrangement + cnt uint8 +} + +func (RegisterWithArrangement) isArg() {} + +func (r RegisterWithArrangement) String() string { + result := r.r.String() + result += r.a.String() + if r.cnt > 0 { + result = "{" + result + if r.cnt == 2 { + r1 := V0 + Reg((uint16(r.r)-uint16(V0)+1)&31) + result += ", " + r1.String() + r.a.String() + } else if r.cnt > 2 { + if (uint16(r.cnt) + ((uint16(r.r) - uint16(V0)) & 31)) > 32 { + for i := 1; i < int(r.cnt); i++ { + cur := V0 + Reg((uint16(r.r)-uint16(V0)+uint16(i))&31) + result += ", " + cur.String() + r.a.String() + } + } else { + r1 := V0 + Reg((uint16(r.r)-uint16(V0)+uint16(r.cnt)-1)&31) + result += "-" + r1.String() + r.a.String() + } + } + result += "}" + } + return result +} + +// Register with arrangement and index: .[], +// { .B, .B }[]. +type RegisterWithArrangementAndIndex struct { + r Reg + a Arrangement + index uint8 + cnt uint8 +} + +func (RegisterWithArrangementAndIndex) isArg() {} + +func (r RegisterWithArrangementAndIndex) String() string { + result := r.r.String() + result += r.a.String() + if r.cnt > 0 { + result = "{" + result + if r.cnt == 2 { + r1 := V0 + Reg((uint16(r.r)-uint16(V0)+1)&31) + result += ", " + r1.String() + r.a.String() + } else if r.cnt > 2 { + if (uint16(r.cnt) + ((uint16(r.r) - uint16(V0)) & 31)) > 32 { + for i := 1; i < int(r.cnt); i++ { + cur := V0 + Reg((uint16(r.r)-uint16(V0)+uint16(i))&31) + result += ", " + cur.String() + r.a.String() + } + } else { + r1 := V0 + Reg((uint16(r.r)-uint16(V0)+uint16(r.cnt)-1)&31) + result += "-" + r1.String() + r.a.String() + } + } + result += "}" + } + return fmt.Sprintf("%s[%d]", result, r.index) +} diff --git a/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/inst.json b/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/inst.json new file mode 100644 index 0000000000..2d25c944a2 --- /dev/null +++ b/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/inst.json @@ -0,0 +1,1219 @@ +[{"Name":"ADC","Bits":"0|0|0|1|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ADC , , ","Code":"","Alias":""}, +{"Name":"ADC","Bits":"1|0|0|1|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ADC , , ","Code":"","Alias":""}, +{"Name":"ADCS","Bits":"0|0|1|1|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ADCS , , ","Code":"","Alias":""}, +{"Name":"ADCS","Bits":"1|0|1|1|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ADCS , , ","Code":"","Alias":""}, +{"Name":"ADD (extended register)","Bits":"0|0|0|0|1|0|1|1|0|0|1|Rm:5|option:3|imm3:3|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ADD , , {, {#}}","Code":"","Alias":""}, +{"Name":"ADD (extended register)","Bits":"1|0|0|0|1|0|1|1|0|0|1|Rm:5|option:3|imm3:3|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ADD , , {, {#}}","Code":"","Alias":""}, +{"Name":"ADD (immediate)","Bits":"0|0|0|1|0|0|0|1|shift:2|imm12:12|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ADD , , #{, }","Code":"","Alias":"This instruction is used by the alias MOV (to/from SP)."}, +{"Name":"ADD (immediate)","Bits":"1|0|0|1|0|0|0|1|shift:2|imm12:12|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ADD , , #{, }","Code":"","Alias":"This instruction is used by the alias MOV (to/from SP)."}, +{"Name":"ADD (shifted register)","Bits":"0|0|0|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ADD , , {, #}","Code":"","Alias":""}, +{"Name":"ADD (shifted register)","Bits":"1|0|0|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ADD , , {, #}","Code":"","Alias":""}, +{"Name":"ADDS (extended register)","Bits":"0|0|1|0|1|0|1|1|0|0|1|Rm:5|option:3|imm3:3|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ADDS , , {, {#}}","Code":"","Alias":"This instruction is used by the alias CMN (extended register)."}, +{"Name":"ADDS (extended register)","Bits":"1|0|1|0|1|0|1|1|0|0|1|Rm:5|option:3|imm3:3|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ADDS , , {, {#}}","Code":"","Alias":"This instruction is used by the alias CMN (extended register)."}, +{"Name":"ADDS (immediate)","Bits":"0|0|1|1|0|0|0|1|shift:2|imm12:12|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ADDS , , #{, }","Code":"","Alias":"This instruction is used by the alias CMN (immediate)."}, +{"Name":"ADDS (immediate)","Bits":"1|0|1|1|0|0|0|1|shift:2|imm12:12|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ADDS , , #{, }","Code":"","Alias":"This instruction is used by the alias CMN (immediate)."}, +{"Name":"ADDS (shifted register)","Bits":"0|0|1|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ADDS , , {, #}","Code":"","Alias":"This instruction is used by the alias CMN (shifted register)."}, +{"Name":"ADDS (shifted register)","Bits":"1|0|1|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ADDS , , {, #}","Code":"","Alias":"This instruction is used by the alias CMN (shifted register)."}, +{"Name":"ADR","Bits":"0|immlo:2|1|0|0|0|0|immhi:19|Rd:5","Arch":"Literal variant","Syntax":"ADR ,