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cmd/compile: fix register masks of ANDCC et al. on PPC64
PPC64's ANDCC, ORCC, XORCC SSA ops produce a flags value, which should not have register mask of an integer register. Fixes #34468. Change-Id: Ic762e423b20275fd9f8118dae7951c258d59738c Reviewed-on: https://go-review.googlesource.com/c/go/+/196960 Reviewed-by: Keith Randall <khr@golang.org>
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@ -566,7 +566,7 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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ssa.OpPPC64ROTL, ssa.OpPPC64ROTLW,
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ssa.OpPPC64MULHD, ssa.OpPPC64MULHW, ssa.OpPPC64MULHDU, ssa.OpPPC64MULHWU,
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ssa.OpPPC64FMUL, ssa.OpPPC64FMULS, ssa.OpPPC64FDIV, ssa.OpPPC64FDIVS, ssa.OpPPC64FCPSGN,
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ssa.OpPPC64AND, ssa.OpPPC64ANDCC, ssa.OpPPC64OR, ssa.OpPPC64ORCC, ssa.OpPPC64ANDN, ssa.OpPPC64ORN, ssa.OpPPC64NOR, ssa.OpPPC64XOR, ssa.OpPPC64XORCC, ssa.OpPPC64EQV:
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ssa.OpPPC64AND, ssa.OpPPC64OR, ssa.OpPPC64ANDN, ssa.OpPPC64ORN, ssa.OpPPC64NOR, ssa.OpPPC64XOR, ssa.OpPPC64EQV:
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r := v.Reg()
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r1 := v.Args[0].Reg()
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r2 := v.Args[1].Reg()
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@ -577,6 +577,16 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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case ssa.OpPPC64ANDCC, ssa.OpPPC64ORCC, ssa.OpPPC64XORCC:
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r1 := v.Args[0].Reg()
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r2 := v.Args[1].Reg()
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p := s.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = r2
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p.Reg = r1
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p.To.Type = obj.TYPE_REG
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p.To.Reg = ppc64.REGTMP // result is not needed
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case ssa.OpPPC64ROTLconst, ssa.OpPPC64ROTLWconst:
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p := s.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_CONST
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@ -252,27 +252,27 @@ func init() {
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{name: "MFVSRD", argLength: 1, reg: fpgp, asm: "MFVSRD", typ: "Int64"}, // move 64 bits of F register into G register
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{name: "MTVSRD", argLength: 1, reg: gpfp, asm: "MTVSRD", typ: "Float64"}, // move 64 bits of G register into F register
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{name: "AND", argLength: 2, reg: gp21, asm: "AND", commutative: true}, // arg0&arg1
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{name: "ANDN", argLength: 2, reg: gp21, asm: "ANDN"}, // arg0&^arg1
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{name: "ANDCC", argLength: 2, reg: gp21, asm: "ANDCC", commutative: true, typ: "Flags"}, // arg0&arg1 sets CC
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{name: "OR", argLength: 2, reg: gp21, asm: "OR", commutative: true}, // arg0|arg1
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{name: "ORN", argLength: 2, reg: gp21, asm: "ORN"}, // arg0|^arg1
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{name: "ORCC", argLength: 2, reg: gp21, asm: "ORCC", commutative: true, typ: "Flags"}, // arg0|arg1 sets CC
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{name: "NOR", argLength: 2, reg: gp21, asm: "NOR", commutative: true}, // ^(arg0|arg1)
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{name: "XOR", argLength: 2, reg: gp21, asm: "XOR", typ: "Int64", commutative: true}, // arg0^arg1
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{name: "XORCC", argLength: 2, reg: gp21, asm: "XORCC", commutative: true, typ: "Flags"}, // arg0^arg1 sets CC
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{name: "EQV", argLength: 2, reg: gp21, asm: "EQV", typ: "Int64", commutative: true}, // arg0^^arg1
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{name: "NEG", argLength: 1, reg: gp11, asm: "NEG"}, // -arg0 (integer)
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{name: "FNEG", argLength: 1, reg: fp11, asm: "FNEG"}, // -arg0 (floating point)
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{name: "FSQRT", argLength: 1, reg: fp11, asm: "FSQRT"}, // sqrt(arg0) (floating point)
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{name: "FSQRTS", argLength: 1, reg: fp11, asm: "FSQRTS"}, // sqrt(arg0) (floating point, single precision)
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{name: "FFLOOR", argLength: 1, reg: fp11, asm: "FRIM"}, // floor(arg0), float64
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{name: "FCEIL", argLength: 1, reg: fp11, asm: "FRIP"}, // ceil(arg0), float64
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{name: "FTRUNC", argLength: 1, reg: fp11, asm: "FRIZ"}, // trunc(arg0), float64
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{name: "FROUND", argLength: 1, reg: fp11, asm: "FRIN"}, // round(arg0), float64
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{name: "FABS", argLength: 1, reg: fp11, asm: "FABS"}, // abs(arg0), float64
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{name: "FNABS", argLength: 1, reg: fp11, asm: "FNABS"}, // -abs(arg0), float64
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{name: "FCPSGN", argLength: 2, reg: fp21, asm: "FCPSGN"}, // copysign arg0 -> arg1, float64
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{name: "AND", argLength: 2, reg: gp21, asm: "AND", commutative: true}, // arg0&arg1
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{name: "ANDN", argLength: 2, reg: gp21, asm: "ANDN"}, // arg0&^arg1
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{name: "ANDCC", argLength: 2, reg: gp2cr, asm: "ANDCC", commutative: true, typ: "Flags"}, // arg0&arg1 sets CC
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{name: "OR", argLength: 2, reg: gp21, asm: "OR", commutative: true}, // arg0|arg1
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{name: "ORN", argLength: 2, reg: gp21, asm: "ORN"}, // arg0|^arg1
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{name: "ORCC", argLength: 2, reg: gp2cr, asm: "ORCC", commutative: true, typ: "Flags"}, // arg0|arg1 sets CC
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{name: "NOR", argLength: 2, reg: gp21, asm: "NOR", commutative: true}, // ^(arg0|arg1)
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{name: "XOR", argLength: 2, reg: gp21, asm: "XOR", typ: "Int64", commutative: true}, // arg0^arg1
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{name: "XORCC", argLength: 2, reg: gp2cr, asm: "XORCC", commutative: true, typ: "Flags"}, // arg0^arg1 sets CC
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{name: "EQV", argLength: 2, reg: gp21, asm: "EQV", typ: "Int64", commutative: true}, // arg0^^arg1
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{name: "NEG", argLength: 1, reg: gp11, asm: "NEG"}, // -arg0 (integer)
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{name: "FNEG", argLength: 1, reg: fp11, asm: "FNEG"}, // -arg0 (floating point)
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{name: "FSQRT", argLength: 1, reg: fp11, asm: "FSQRT"}, // sqrt(arg0) (floating point)
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{name: "FSQRTS", argLength: 1, reg: fp11, asm: "FSQRTS"}, // sqrt(arg0) (floating point, single precision)
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{name: "FFLOOR", argLength: 1, reg: fp11, asm: "FRIM"}, // floor(arg0), float64
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{name: "FCEIL", argLength: 1, reg: fp11, asm: "FRIP"}, // ceil(arg0), float64
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{name: "FTRUNC", argLength: 1, reg: fp11, asm: "FRIZ"}, // trunc(arg0), float64
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{name: "FROUND", argLength: 1, reg: fp11, asm: "FRIN"}, // round(arg0), float64
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{name: "FABS", argLength: 1, reg: fp11, asm: "FABS"}, // abs(arg0), float64
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{name: "FNABS", argLength: 1, reg: fp11, asm: "FNABS"}, // -abs(arg0), float64
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{name: "FCPSGN", argLength: 2, reg: fp21, asm: "FCPSGN"}, // copysign arg0 -> arg1, float64
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{name: "ORconst", argLength: 1, reg: gp11, asm: "OR", aux: "Int64"}, // arg0|aux
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{name: "XORconst", argLength: 1, reg: gp11, asm: "XOR", aux: "Int64"}, // arg0^aux
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@ -23026,9 +23026,6 @@ var opcodeTable = [...]opInfo{
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{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
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{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
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},
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outputs: []outputInfo{
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{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
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},
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},
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},
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{
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@ -23070,9 +23067,6 @@ var opcodeTable = [...]opInfo{
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{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
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{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
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},
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outputs: []outputInfo{
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{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
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},
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},
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},
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{
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@ -23115,9 +23109,6 @@ var opcodeTable = [...]opInfo{
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{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
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{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
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},
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outputs: []outputInfo{
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{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
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},
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},
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},
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{
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