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https://github.com/golang/go
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cmd/internal/obj/loong64: add atomic memory access instructions support
The AM* atomic access instruction performs a sequence of “read-modify-write”
operations on a memory cell atomically. Specifically, it retrieves the old
value at the specified address in memory and writes it to the general register
rd, performs some simple operations on the old value in memory and the value
in the general register rk, and then write the result of the operation back
to the memory address pointed to by general register rj.
Go asm syntax:
AM{SWAP/ADD/AND/OR/XOR/MAX/MIN}[DB]{W/V} RK, (RJ), RD
AM{MAX/MIN}[DB]{WU/VU} RK, (RJ), RD
Equivalent platform assembler syntax:
am{swap/add/and/or/xor/max/min}[_db].{w/d} rd, rk, rj
am{max/min}[_db].{wu/du} rd, rk, rj
Ref: https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html
Change-Id: I99ea4553ae731675180d63691c19ef334e7e7817
Reviewed-on: https://go-review.googlesource.com/c/go/+/481577
Reviewed-by: Meidan Li <limeidan@loongson.cn>
Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn>
Reviewed-by: Mauri de Souza Meneguzzo <mauri870@gmail.com>
Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
Reviewed-by: Qiqi Huang <huangqiqi@loongson.cn>
Reviewed-by: WANG Xuerui <git@xen0n.name>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: Cherry Mui <cherryyz@google.com>
This commit is contained in:
Guoqi Chen
Cherry Mui
parent
ca17bda856
commit
504212bbd7
@ -55,6 +55,10 @@ func IsLoong64RDTIME(op obj.As) bool {
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return false
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}
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func IsLoong64AMO(op obj.As) bool {
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return loong64.IsAtomicInst(op)
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}
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func loong64RegisterNumber(name string, n int16) (int16, bool) {
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switch name {
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case "F":
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@ -669,9 +669,17 @@ func (p *Parser) asmInstruction(op obj.As, cond string, a []obj.Addr) {
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prog.Reg = p.getRegister(prog, op, &a[1])
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prog.To = a[2]
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case sys.Loong64:
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switch {
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// Loong64 atomic instructions with one input and two outputs.
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case arch.IsLoong64AMO(op):
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prog.From = a[0]
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prog.To = a[1]
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prog.RegTo2 = a[2].Reg
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default:
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prog.From = a[0]
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prog.Reg = p.getRegister(prog, op, &a[1])
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prog.To = a[2]
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}
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case sys.ARM:
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// Special cases.
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if arch.IsARMSTREX(op) {
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50
src/cmd/asm/internal/asm/testdata/loong64enc1.s
vendored
50
src/cmd/asm/internal/asm/testdata/loong64enc1.s
vendored
@ -231,3 +231,53 @@ lable2:
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MOVV FCC0, R4 // 04dc1401
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MOVV R4, FCC0 // 80d81401
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// Loong64 atomic memory access instructions
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AMSWAPB R14, (R13), R12 // ac395c38
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AMSWAPH R14, (R13), R12 // acb95c38
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AMSWAPW R14, (R13), R12 // ac396038
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AMSWAPV R14, (R13), R12 // acb96038
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AMCASB R14, (R13), R12 // ac395838
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AMCASH R14, (R13), R12 // acb95838
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AMCASW R14, (R13), R12 // ac395938
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AMCASV R14, (R13), R12 // acb95938
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AMADDW R14, (R13), R12 // ac396138
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AMADDV R14, (R13), R12 // acb96138
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AMANDW R14, (R13), R12 // ac396238
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AMANDV R14, (R13), R12 // acb96238
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AMORW R14, (R13), R12 // ac396338
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AMORV R14, (R13), R12 // acb96338
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AMXORW R14, (R13), R12 // ac396438
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AMXORV R14, (R13), R12 // acb96438
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AMMAXW R14, (R13), R12 // ac396538
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AMMAXV R14, (R13), R12 // acb96538
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AMMINW R14, (R13), R12 // ac396638
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AMMINV R14, (R13), R12 // acb96638
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AMMAXWU R14, (R13), R12 // ac396738
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AMMAXVU R14, (R13), R12 // acb96738
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AMMINWU R14, (R13), R12 // ac396838
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AMMINVU R14, (R13), R12 // acb96838
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AMSWAPDBB R14, (R13), R12 // ac395e38
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AMSWAPDBH R14, (R13), R12 // acb95e38
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AMSWAPDBW R14, (R13), R12 // ac396938
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AMSWAPDBV R14, (R13), R12 // acb96938
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AMCASDBB R14, (R13), R12 // ac395a38
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AMCASDBH R14, (R13), R12 // acb95a38
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AMCASDBW R14, (R13), R12 // ac395b38
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AMCASDBV R14, (R13), R12 // acb95b38
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AMADDDBW R14, (R13), R12 // ac396a38
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AMADDDBV R14, (R13), R12 // acb96a38
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AMANDDBW R14, (R13), R12 // ac396b38
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AMANDDBV R14, (R13), R12 // acb96b38
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AMORDBW R14, (R13), R12 // ac396c38
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AMORDBV R14, (R13), R12 // acb96c38
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AMXORDBW R14, (R13), R12 // ac396d38
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AMXORDBV R14, (R13), R12 // acb96d38
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AMMAXDBW R14, (R13), R12 // ac396e38
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AMMAXDBV R14, (R13), R12 // acb96e38
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AMMINDBW R14, (R13), R12 // ac396f38
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AMMINDBV R14, (R13), R12 // acb96f38
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AMMAXDBWU R14, (R13), R12 // ac397038
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AMMAXDBVU R14, (R13), R12 // acb97038
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AMMINDBWU R14, (R13), R12 // ac397138
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AMMINDBVU R14, (R13), R12 // acb97138
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@ -394,6 +394,56 @@ const (
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AMOVVF
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AMOVVD
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// 2.2.7. Atomic Memory Access Instructions
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AAMSWAPB
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AAMSWAPH
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AAMSWAPW
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AAMSWAPV
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AAMCASB
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AAMCASH
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AAMCASW
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AAMCASV
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AAMADDW
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AAMADDV
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AAMANDW
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AAMANDV
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AAMORW
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AAMORV
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AAMXORW
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AAMXORV
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AAMMAXW
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AAMMAXV
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AAMMINW
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AAMMINV
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AAMMAXWU
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AAMMAXVU
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AAMMINWU
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AAMMINVU
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AAMSWAPDBB
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AAMSWAPDBH
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AAMSWAPDBW
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AAMSWAPDBV
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AAMCASDBB
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AAMCASDBH
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AAMCASDBW
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AAMCASDBV
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AAMADDDBW
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AAMADDDBV
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AAMANDDBW
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AAMANDDBV
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AAMORDBW
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AAMORDBV
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AAMXORDBW
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AAMXORDBV
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AAMMAXDBW
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AAMMAXDBV
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AAMMINDBW
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AAMMINDBV
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AAMMAXDBWU
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AAMMAXDBVU
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AAMMINDBWU
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AAMMINDBVU
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// 2.2.10. Other Miscellaneous Instructions
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ARDTIMELW
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ARDTIMEHW
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@ -131,6 +131,54 @@ var Anames = []string{
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"MOVDV",
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"MOVVF",
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"MOVVD",
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"AMSWAPB",
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"AMSWAPH",
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"AMSWAPW",
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"AMSWAPV",
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"AMCASB",
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"AMCASH",
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"AMCASW",
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"AMCASV",
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"AMADDW",
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"AMADDV",
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"AMANDW",
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"AMANDV",
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"AMORW",
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"AMORV",
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"AMXORW",
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"AMXORV",
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"AMMAXW",
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"AMMAXV",
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"AMMINW",
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"AMMINV",
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"AMMAXWU",
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"AMMAXVU",
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"AMMINWU",
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"AMMINVU",
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"AMSWAPDBB",
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"AMSWAPDBH",
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"AMSWAPDBW",
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"AMSWAPDBV",
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"AMCASDBB",
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"AMCASDBH",
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"AMCASDBW",
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"AMCASDBV",
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"AMADDDBW",
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"AMADDDBV",
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"AMANDDBW",
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"AMANDDBV",
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"AMORDBW",
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"AMORDBV",
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"AMXORDBW",
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"AMXORDBV",
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"AMMAXDBW",
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"AMMAXDBV",
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"AMMINDBW",
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"AMMINDBV",
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"AMMAXDBWU",
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"AMMAXDBVU",
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"AMMINDBWU",
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"AMMINDBVU",
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"RDTIMELW",
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"RDTIMEHW",
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"RDTIMED",
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@ -356,7 +356,7 @@ var optab = []Optab{
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{ATEQ, C_SCON, C_NONE, C_NONE, C_REG, C_NONE, 15, 8, 0, 0},
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{ARDTIMELW, C_NONE, C_NONE, C_NONE, C_REG, C_REG, 62, 4, 0, 0},
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{AAMSWAPW, C_REG, C_NONE, C_NONE, C_ZOREG, C_REG, 66, 4, 0, 0},
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{ANOOP, C_NONE, C_NONE, C_NONE, C_NONE, C_NONE, 49, 4, 0, 0},
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{obj.APCALIGN, C_SCON, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0},
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@ -374,6 +374,63 @@ var optab = []Optab{
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{obj.AXXX, C_NONE, C_NONE, C_NONE, C_NONE, C_NONE, 0, 4, 0, 0},
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}
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var atomicInst = map[obj.As]uint32{
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AAMSWAPB: 0x070B8 << 15, // amswap.b
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AAMSWAPH: 0x070B9 << 15, // amswap.h
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AAMSWAPW: 0x070C0 << 15, // amswap.w
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AAMSWAPV: 0x070C1 << 15, // amswap.d
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AAMCASB: 0x070B0 << 15, // amcas.b
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AAMCASH: 0x070B1 << 15, // amcas.h
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AAMCASW: 0x070B2 << 15, // amcas.w
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AAMCASV: 0x070B3 << 15, // amcas.d
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AAMADDW: 0x070C2 << 15, // amadd.w
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AAMADDV: 0x070C3 << 15, // amadd.d
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AAMANDW: 0x070C4 << 15, // amand.w
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AAMANDV: 0x070C5 << 15, // amand.d
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AAMORW: 0x070C6 << 15, // amor.w
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AAMORV: 0x070C7 << 15, // amor.d
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AAMXORW: 0x070C8 << 15, // amxor.w
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AAMXORV: 0x070C9 << 15, // amxor.d
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AAMMAXW: 0x070CA << 15, // ammax.w
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AAMMAXV: 0x070CB << 15, // ammax.d
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AAMMINW: 0x070CC << 15, // ammin.w
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AAMMINV: 0x070CD << 15, // ammin.d
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AAMMAXWU: 0x070CE << 15, // ammax.wu
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AAMMAXVU: 0x070CF << 15, // ammax.du
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AAMMINWU: 0x070D0 << 15, // ammin.wu
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AAMMINVU: 0x070D1 << 15, // ammin.du
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AAMSWAPDBB: 0x070BC << 15, // amswap_db.b
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AAMSWAPDBH: 0x070BD << 15, // amswap_db.h
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AAMSWAPDBW: 0x070D2 << 15, // amswap_db.w
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AAMSWAPDBV: 0x070D3 << 15, // amswap_db.d
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AAMCASDBB: 0x070B4 << 15, // amcas_db.b
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AAMCASDBH: 0x070B5 << 15, // amcas_db.h
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AAMCASDBW: 0x070B6 << 15, // amcas_db.w
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AAMCASDBV: 0x070B7 << 15, // amcas_db.d
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AAMADDDBW: 0x070D4 << 15, // amadd_db.w
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AAMADDDBV: 0x070D5 << 15, // amadd_db.d
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AAMANDDBW: 0x070D6 << 15, // amand_db.w
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AAMANDDBV: 0x070D7 << 15, // amand_db.d
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AAMORDBW: 0x070D8 << 15, // amor_db.w
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AAMORDBV: 0x070D9 << 15, // amor_db.d
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AAMXORDBW: 0x070DA << 15, // amxor_db.w
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AAMXORDBV: 0x070DB << 15, // amxor_db.d
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AAMMAXDBW: 0x070DC << 15, // ammax_db.w
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AAMMAXDBV: 0x070DD << 15, // ammax_db.d
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AAMMINDBW: 0x070DE << 15, // ammin_db.w
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AAMMINDBV: 0x070DF << 15, // ammin_db.d
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AAMMAXDBWU: 0x070E0 << 15, // ammax_db.wu
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AAMMAXDBVU: 0x070E1 << 15, // ammax_db.du
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AAMMINDBWU: 0x070E2 << 15, // ammin_db.wu
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AAMMINDBVU: 0x070E3 << 15, // ammin_db.du
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}
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func IsAtomicInst(as obj.As) bool {
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_, ok := atomicInst[as]
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return ok
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}
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// pcAlignPadLength returns the number of bytes required to align pc to alignedValue,
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// reporting an error if alignedValue is not a power of two or is out of range.
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func pcAlignPadLength(ctxt *obj.Link, pc int64, alignedValue int64) int {
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@ -1182,6 +1239,14 @@ func buildop(ctxt *obj.Link) {
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case ANOOP:
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opset(obj.AUNDEF, r0)
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case AAMSWAPW:
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for i := range atomicInst {
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if i == AAMSWAPW {
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continue
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}
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opset(i, r0)
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}
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}
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}
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}
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@ -1817,6 +1882,18 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) {
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rel2.Sym = p.From.Sym
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rel2.Type = objabi.R_LOONG64_GOT_LO
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rel2.Add = 0x0
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case 66: // am* From, To, RegTo2 ==> am* RegTo2, From, To
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rk := p.From.Reg
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rj := p.To.Reg
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rd := p.RegTo2
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// See section 2.2.7.1 of https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html
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// for the register usage constraints.
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if rd == rj || rd == rk {
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c.ctxt.Diag("illegal register combination: %v\n", p)
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}
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o1 = OP_RRR(atomicInst[p.As], uint32(rk), uint32(rj), uint32(rd))
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}
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out[0] = o1
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