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cmd/internal/obj/riscv: support additional register to register moves
Add support for signed and unsigned register to register moves of various sizes. This makes it easier to handle zero and sign extension and will allow for further changes that improve the compiler optimisations for riscv64. While here, change the existing register to register moves from obj.Prog rewriting to instruction generation. Change-Id: Id21911019b76922367a134da13c3449a84a1fb08 Reviewed-on: https://go-review.googlesource.com/c/go/+/264657 Trust: Joel Sing <joel@sing.id.au> Reviewed-by: Cherry Zhang <cherryyz@google.com>
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parent
05b6118139
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29
src/cmd/asm/internal/asm/testdata/riscvenc.s
vendored
29
src/cmd/asm/internal/asm/testdata/riscvenc.s
vendored
@ -297,6 +297,13 @@ start:
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MOVW X5, (X6) // 23205300
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MOVW X5, 4(X6) // 23225300
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MOVB X5, X6 // 1393820313538343
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MOVH X5, X6 // 1393020313530343
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MOVW X5, X6 // 1b830200
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MOVBU X5, X6 // 13f3f20f
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MOVHU X5, X6 // 1393020313530303
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MOVWU X5, X6 // 1393020213530302
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MOVF 4(X5), F0 // 07a04200
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MOVF F0, 4(X5) // 27a20200
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MOVF F0, F1 // d3000020
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@ -318,7 +325,7 @@ start:
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// These jumps can get printed as jumps to 2 because they go to the
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// second instruction in the function (the first instruction is an
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// invisible stack pointer adjustment).
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JMP start // JMP 2 // 6ff01fc5
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JMP start // JMP 2 // 6ff09fc2
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JMP (X5) // 67800200
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JMP 4(X5) // 67804200
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@ -331,16 +338,16 @@ start:
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JMP asmtest(SB) // 970f0000
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// Branch pseudo-instructions
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BEQZ X5, start // BEQZ X5, 2 // e38a02c2
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BGEZ X5, start // BGEZ X5, 2 // e3d802c2
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BGT X5, X6, start // BGT X5, X6, 2 // e3c662c2
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BGTU X5, X6, start // BGTU X5, X6, 2 // e3e462c2
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BGTZ X5, start // BGTZ X5, 2 // e34250c2
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BLE X5, X6, start // BLE X5, X6, 2 // e3d062c2
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BLEU X5, X6, start // BLEU X5, X6, 2 // e3fe62c0
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BLEZ X5, start // BLEZ X5, 2 // e35c50c0
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BLTZ X5, start // BLTZ X5, 2 // e3ca02c0
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BNEZ X5, start // BNEZ X5, 2 // e39802c0
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BEQZ X5, start // BEQZ X5, 2 // e38602c0
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BGEZ X5, start // BGEZ X5, 2 // e3d402c0
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BGT X5, X6, start // BGT X5, X6, 2 // e3c262c0
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BGTU X5, X6, start // BGTU X5, X6, 2 // e3e062c0
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BGTZ X5, start // BGTZ X5, 2 // e34e50be
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BLE X5, X6, start // BLE X5, X6, 2 // e3dc62be
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BLEU X5, X6, start // BLEU X5, X6, 2 // e3fa62be
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BLEZ X5, start // BLEZ X5, 2 // e35850be
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BLTZ X5, start // BLTZ X5, 2 // e3c602be
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BNEZ X5, start // BNEZ X5, 2 // e39402be
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// Set pseudo-instructions
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SEQZ X15, X15 // 93b71700
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@ -252,19 +252,7 @@ func rewriteMOV(ctxt *obj.Link, newprog obj.ProgAlloc, p *obj.Prog) {
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switch p.To.Type {
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case obj.TYPE_REG:
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switch p.As {
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case AMOV: // MOV Ra, Rb -> ADDI $0, Ra, Rb
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p.As = AADDI
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p.Reg = p.From.Reg
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p.From = obj.Addr{Type: obj.TYPE_CONST}
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case AMOVF: // MOVF Ra, Rb -> FSGNJS Ra, Ra, Rb
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p.As = AFSGNJS
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p.Reg = p.From.Reg
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case AMOVD: // MOVD Ra, Rb -> FSGNJD Ra, Ra, Rb
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p.As = AFSGNJD
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p.Reg = p.From.Reg
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case AMOV, AMOVB, AMOVH, AMOVW, AMOVBU, AMOVHU, AMOVWU, AMOVF, AMOVD:
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default:
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ctxt.Diag("unsupported register-register move at %v", p)
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}
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@ -1805,6 +1793,44 @@ func instructionsForProg(p *obj.Prog) []*instruction {
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}
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ins.imm = p.To.Offset
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case AMOV, AMOVB, AMOVH, AMOVW, AMOVBU, AMOVHU, AMOVWU, AMOVF, AMOVD:
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// Handle register to register moves.
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if p.From.Type != obj.TYPE_REG || p.To.Type != obj.TYPE_REG {
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break
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}
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switch p.As {
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case AMOV: // MOV Ra, Rb -> ADDI $0, Ra, Rb
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ins.as, ins.rs1, ins.rs2, ins.imm = AADDI, uint32(p.From.Reg), obj.REG_NONE, 0
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case AMOVW: // MOVW Ra, Rb -> ADDIW $0, Ra, Rb
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ins.as, ins.rs1, ins.rs2, ins.imm = AADDIW, uint32(p.From.Reg), obj.REG_NONE, 0
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case AMOVBU: // MOVBU Ra, Rb -> ANDI $255, Ra, Rb
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ins.as, ins.rs1, ins.rs2, ins.imm = AANDI, uint32(p.From.Reg), obj.REG_NONE, 255
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case AMOVF: // MOVF Ra, Rb -> FSGNJS Ra, Ra, Rb
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ins.as, ins.rs1 = AFSGNJS, uint32(p.From.Reg)
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case AMOVD: // MOVD Ra, Rb -> FSGNJD Ra, Ra, Rb
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ins.as, ins.rs1 = AFSGNJD, uint32(p.From.Reg)
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case AMOVB, AMOVH:
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// Use SLLI/SRAI to extend.
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ins.as, ins.rs1, ins.rs2 = ASLLI, uint32(p.From.Reg), obj.REG_NONE
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if p.As == AMOVB {
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ins.imm = 56
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} else if p.As == AMOVH {
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ins.imm = 48
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}
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ins2 := &instruction{as: ASRAI, rd: ins.rd, rs1: ins.rd, imm: ins.imm}
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inss = append(inss, ins2)
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case AMOVHU, AMOVWU:
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// Use SLLI/SRLI to extend.
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ins.as, ins.rs1, ins.rs2 = ASLLI, uint32(p.From.Reg), obj.REG_NONE
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if p.As == AMOVHU {
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ins.imm = 48
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} else if p.As == AMOVWU {
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ins.imm = 32
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}
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ins2 := &instruction{as: ASRLI, rd: ins.rd, rs1: ins.rd, imm: ins.imm}
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inss = append(inss, ins2)
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}
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case ALW, ALWU, ALH, ALHU, ALB, ALBU, ALD, AFLW, AFLD:
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if p.From.Type != obj.TYPE_MEM {
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p.Ctxt.Diag("%v requires memory for source", p)
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@ -1859,13 +1885,13 @@ func instructionsForProg(p *obj.Prog) []*instruction {
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} else {
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ins.as = AFEQD
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}
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ins = &instruction{
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ins2 := &instruction{
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as: AXORI, // [bit] xor 1 = not [bit]
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rd: ins.rd,
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rs1: ins.rd,
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imm: 1,
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}
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inss = append(inss, ins)
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inss = append(inss, ins2)
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case AFSQRTS, AFSQRTD:
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// These instructions expect a zero (i.e. float register 0)
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