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cmd/internal/obj,cmd/asm: add vector registers to riscv64 assembler

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This adds V0 through V31 as vector registers, which are available on CPUs
that support the V extension.

Change-Id: Ibffee3f9a2cf1d062638715b3744431d72d451ce
Reviewed-on: https://go-review.googlesource.com/c/go/+/595404
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: Cherry Mui <cherryyz@google.com>
Reviewed-by: Mark Ryan <markdryan@rivosinc.com>
Reviewed-by: Michael Pratt <mpratt@google.com>
Reviewed-by: 鹏程汪 <wangpengcheng.pp@bytedance.com>
This commit is contained in:
Joel Sing 2024-06-28 00:03:53 +10:00
parent 77c53c16e9
commit 4646556ba4
4 changed files with 51 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/cmd/asm/internal/arch/arch.go
View File

@ -586,6 +586,10 @@ func archRISCV64(shared bool) *Arch {
name := fmt.Sprintf("F%d", i-riscv.REG_F0)
register[name] = int16(i)
}
for i := riscv.REG_V0; i <= riscv.REG_V31; i++ {
name := fmt.Sprintf("V%d", i-riscv.REG_V0)
register[name] = int16(i)
}
// General registers with ABI names.
register["ZERO"] = riscv.REG_ZERO

36
src/cmd/internal/obj/riscv/cpu.go
View File

@ -72,7 +72,7 @@ const (
REG_X30
REG_X31
// FP register numberings.
// Floating Point register numberings.
REG_F0
REG_F1
REG_F2
@ -106,6 +106,40 @@ const (
REG_F30
REG_F31
// Vector register numberings.
REG_V0
REG_V1
REG_V2
REG_V3
REG_V4
REG_V5
REG_V6
REG_V7
REG_V8
REG_V9
REG_V10
REG_V11
REG_V12
REG_V13
REG_V14
REG_V15
REG_V16
REG_V17
REG_V18
REG_V19
REG_V20
REG_V21
REG_V22
REG_V23
REG_V24
REG_V25
REG_V26
REG_V27
REG_V28
REG_V29
REG_V30
REG_V31
// This marks the end of the register numbering.
REG_END

2
src/cmd/internal/obj/riscv/list.go
View File

@ -28,6 +28,8 @@ func RegName(r int) string {
return fmt.Sprintf("X%d", r-REG_X0)
case REG_F0 <= r && r <= REG_F31:
return fmt.Sprintf("F%d", r-REG_F0)
case REG_V0 <= r && r <= REG_V31:
return fmt.Sprintf("V%d", r-REG_V0)
default:
return fmt.Sprintf("Rgok(%d)", r-obj.RBaseRISCV)
}

10
src/cmd/internal/obj/riscv/obj.go
View File

@ -1030,6 +1030,11 @@ func regF(r uint32) uint32 {
return regVal(r, REG_F0, REG_F31)
}
// regV returns a vector register.
func regV(r uint32) uint32 {
return regVal(r, REG_V0, REG_V31)
}
// regAddr extracts a register from an Addr.
func regAddr(a obj.Addr, min, max uint32) uint32 {
if a.Type != obj.TYPE_REG {
@ -1112,6 +1117,11 @@ func wantFloatReg(ctxt *obj.Link, ins *instruction, pos string, r uint32) {
wantReg(ctxt, ins, pos, "float", r, REG_F0, REG_F31)
}
// wantVectorReg checks that r is a vector register.
func wantVectorReg(ctxt *obj.Link, ins *instruction, pos string, r uint32) {
wantReg(ctxt, ins, pos, "vector", r, REG_V0, REG_V31)
}
// wantEvenOffset checks that the offset is a multiple of two.
func wantEvenOffset(ctxt *obj.Link, ins *instruction, offset int64) {
if err := immEven(offset); err != nil {