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https://github.com/golang/go
synced 2024-11-18 13:44:48 -07:00
cmd/asm, cmd/internal/obj/s390x: add new s390x instructions for SSA
This commit adds the following instructions to support the new SSA backend for s390x: 32-bit operations: ADDW SUBW NEGW FNEGS Conditional moves: MOVDEQ MOVDGE MOVDGT MOVDLE MOVDLT MOVDNE Unordered branches (for floating point comparisons): BLEU BLTU Modulo operations: MODW MODWU MODD MODDU The modulo operations might be removed in a future commit because I'd like to change DIV to produce a tuple once the old backend is removed. This commit also removes uses of REGZERO from the assembler. They aren't necessary and R0 will be used as a GPR by SSA. Change-Id: I05756c1cbb74bf4a35fc492f8f0cd34b50763dc9 Reviewed-on: https://go-review.googlesource.com/29075 Run-TryBot: Michael Munday <munday@ca.ibm.com> Reviewed-by: Brad Fitzpatrick <bradfitz@golang.org> TryBot-Result: Gobot Gobot <gobot@golang.org>
This commit is contained in:
parent
dfc56a4cd3
commit
43bdfa9337
35
src/cmd/asm/internal/asm/testdata/s390x.s
vendored
35
src/cmd/asm/internal/asm/testdata/s390x.s
vendored
@ -13,6 +13,13 @@ TEXT main·foo(SB),7,$16-0 // TEXT main.foo(SB), 7, $16-0
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MOVDBR R1, R2 // b90f0021
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MOVWBR R3, R4 // b91f0043
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MOVDEQ R0, R1 // b9e28010
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MOVDGE R2, R3 // b9e2a032
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MOVDGT R4, R5 // b9e22054
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MOVDLE R6, R7 // b9e2c076
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MOVDLT R8, R9 // b9e24098
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MOVDNE R10, R11 // b9e270ba
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MOVD (R15), R1 // e310f0000004
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MOVW (R15), R2 // e320f0000014
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MOVH (R15), R3 // e330f0000015
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@ -50,6 +57,10 @@ TEXT main·foo(SB),7,$16-0 // TEXT main.foo(SB), 7, $16-0
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ADDC R1, R2 // b9ea1022
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ADDC $1, R1, R2 // b9040021c22a00000001
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ADDC R1, R2, R3 // b9ea1032
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ADDW R1, R2 // 1a21
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ADDW R1, R2, R3 // b9f81032
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ADDW $8192, R1 // c21900002000
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ADDW $8192, R1, R2 // ec21200000d8
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SUB R3, R4 // b9090043
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SUB R3, R4, R5 // b9e93054
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SUB $8192, R3 // c238ffffe000
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@ -57,6 +68,10 @@ TEXT main·foo(SB),7,$16-0 // TEXT main.foo(SB), 7, $16-0
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SUBC R1, R2 // b90b0021
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SUBC $1, R1, R2 // b9040021c22affffffff
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SUBC R2, R3, R4 // b9eb2043
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SUBW R3, R4 // 1b43
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SUBW R3, R4, R5 // b9f93054
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SUBW $8192, R1 // c21500002000
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SUBW $8192, R1, R2 // 1821c22500002000
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MULLW R6, R7 // b91c0076
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MULLW R6, R7, R8 // b9040087b91c0086
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MULLW $8192, R6 // a76d2000
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@ -73,10 +88,22 @@ TEXT main·foo(SB),7,$16-0 // TEXT main.foo(SB), 7, $16-0
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DIVD R1, R2, R3 // b90400b2b90d00a1b904003b
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DIVW R4, R5 // b90400b5b91d00a4b904005b
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DIVW R4, R5, R6 // b90400b5b91d00a4b904006b
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DIVDU R7, R8 // b90400a0b90400b8b98700a7b904008b
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DIVDU R7, R8, R9 // b90400a0b90400b8b98700a7b904009b
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DIVWU R1, R2 // b90400a0b90400b2b99700a1b904002b
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DIVWU R1, R2, R3 // b90400a0b90400b2b99700a1b904003b
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DIVDU R7, R8 // a7a90000b90400b8b98700a7b904008b
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DIVDU R7, R8, R9 // a7a90000b90400b8b98700a7b904009b
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DIVWU R1, R2 // a7a90000b90400b2b99700a1b904002b
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DIVWU R1, R2, R3 // a7a90000b90400b2b99700a1b904003b
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MODD R1, R2 // b90400b2b90d00a1b904002a
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MODD R1, R2, R3 // b90400b2b90d00a1b904003a
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MODW R4, R5 // b90400b5b91d00a4b904005a
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MODW R4, R5, R6 // b90400b5b91d00a4b904006a
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MODDU R7, R8 // a7a90000b90400b8b98700a7b904008a
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MODDU R7, R8, R9 // a7a90000b90400b8b98700a7b904009a
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MODWU R1, R2 // a7a90000b90400b2b99700a1b904002a
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MODWU R1, R2, R3 // a7a90000b90400b2b99700a1b904003a
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NEG R1 // b9030011
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NEG R1, R2 // b9030021
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NEGW R1 // b9130011
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NEGW R1, R2 // b9130021
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LAA R1, R2, 524287(R3) // eb213fff7ff8
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LAAG R4, R5, -524288(R6) // eb54600080e8
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@ -212,10 +212,15 @@ const (
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AADDME
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AADDE
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AADDZE
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AADDW
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ADIVW
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ADIVWU
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ADIVD
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ADIVDU
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AMODW
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AMODWU
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AMODD
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AMODDU
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AMULLW
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AMULLD
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AMULHD
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@ -226,7 +231,9 @@ const (
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ASUBV
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ASUBE
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ASUBZE
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ASUBW
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ANEG
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ANEGW
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// integer moves
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AMOVWBR
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@ -240,6 +247,14 @@ const (
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AMOVD
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AMOVDBR
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// conditional moves
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AMOVDEQ
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AMOVDGE
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AMOVDGT
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AMOVDLE
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AMOVDLT
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AMOVDNE
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// integer bitwise
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AAND
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AANDN
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@ -276,6 +291,7 @@ const (
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AFMULS
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AFNABS
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AFNEG
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AFNEGS
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AFNMADD
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AFNMADDS
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AFNMSUB
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@ -334,6 +350,8 @@ const (
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ABGT
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ABLE
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ABLT
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ABLEU
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ABLTU
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ABNE
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ABVC
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ABVS
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@ -11,10 +11,15 @@ var Anames = []string{
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"ADDME",
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"ADDE",
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"ADDZE",
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"ADDW",
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"DIVW",
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"DIVWU",
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"DIVD",
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"DIVDU",
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"MODW",
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"MODWU",
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"MODD",
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"MODDU",
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"MULLW",
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"MULLD",
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"MULHD",
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@ -25,7 +30,9 @@ var Anames = []string{
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"SUBV",
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"SUBE",
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"SUBZE",
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"SUBW",
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"NEG",
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"NEGW",
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"MOVWBR",
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"MOVB",
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"MOVBZ",
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@ -36,6 +43,12 @@ var Anames = []string{
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"MOVWZ",
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"MOVD",
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"MOVDBR",
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"MOVDEQ",
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"MOVDGE",
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"MOVDGT",
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"MOVDLE",
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"MOVDLT",
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"MOVDNE",
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"AND",
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"ANDN",
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"NAND",
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@ -69,6 +82,7 @@ var Anames = []string{
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"FMULS",
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"FNABS",
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"FNEG",
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"FNEGS",
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"FNMADD",
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"FNMADDS",
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"FNMSUB",
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@ -111,6 +125,8 @@ var Anames = []string{
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"BGT",
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"BLE",
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"BLT",
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"BLEU",
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"BLTU",
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"BNE",
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"BVC",
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"BVS",
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@ -145,10 +145,10 @@ var optab = []Optab{
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Optab{AADD, C_REG, C_NONE, C_NONE, C_REG, 2, 0},
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Optab{AADD, C_LCON, C_REG, C_NONE, C_REG, 22, 0},
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Optab{AADD, C_LCON, C_NONE, C_NONE, C_REG, 22, 0},
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Optab{ASUB, C_LCON, C_REG, C_NONE, C_REG, 22, 0},
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Optab{ASUB, C_LCON, C_NONE, C_NONE, C_REG, 22, 0},
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Optab{AMULHD, C_REG, C_NONE, C_NONE, C_REG, 4, 0},
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Optab{AMULHD, C_REG, C_REG, C_NONE, C_REG, 4, 0},
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Optab{ASUBC, C_REG, C_REG, C_NONE, C_REG, 10, 0},
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Optab{ASUBC, C_REG, C_NONE, C_NONE, C_REG, 10, 0},
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Optab{ADIVW, C_REG, C_REG, C_NONE, C_REG, 2, 0},
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Optab{ADIVW, C_REG, C_NONE, C_NONE, C_REG, 2, 0},
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Optab{ASUB, C_REG, C_REG, C_NONE, C_REG, 10, 0},
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@ -217,6 +217,9 @@ var optab = []Optab{
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Optab{ACMPUBEQ, C_REG, C_REG, C_NONE, C_SBRA, 89, 0},
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Optab{ACMPUBEQ, C_REG, C_NONE, C_ANDCON, C_SBRA, 90, 0},
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// move on condition
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Optab{AMOVDEQ, C_REG, C_NONE, C_NONE, C_REG, 17, 0},
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// compare
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Optab{ACMP, C_REG, C_NONE, C_NONE, C_REG, 70, 0},
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Optab{ACMP, C_REG, C_NONE, C_NONE, C_LCON, 71, 0},
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@ -790,6 +793,7 @@ func buildop(ctxt *obj.Link) {
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switch r {
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case AADD:
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opset(AADDC, r)
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opset(AADDW, r)
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opset(AMULLD, r)
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opset(AMULLW, r)
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case ADIVW:
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@ -797,6 +801,10 @@ func buildop(ctxt *obj.Link) {
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opset(ADIVD, r)
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opset(ADIVDU, r)
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opset(ADIVWU, r)
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opset(AMODD, r)
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opset(AMODDU, r)
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opset(AMODW, r)
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opset(AMODWU, r)
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case AMULHD:
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opset(AMULHDU, r)
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case AMOVBZ:
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@ -844,6 +852,8 @@ func buildop(ctxt *obj.Link) {
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opset(ABNE, r)
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opset(ABVC, r)
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opset(ABVS, r)
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opset(ABLEU, r)
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opset(ABLTU, r)
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case ABR:
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opset(ABL, r)
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case ABC:
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@ -851,6 +861,7 @@ func buildop(ctxt *obj.Link) {
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case AFABS:
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opset(AFNABS, r)
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opset(AFNEG, r)
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opset(AFNEGS, r)
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opset(ALEDBR, r)
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opset(ALDEBR, r)
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opset(AFSQRT, r)
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@ -889,6 +900,9 @@ func buildop(ctxt *obj.Link) {
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case ASUB:
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opset(ASUBC, r)
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opset(ASUBE, r)
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opset(ASUBW, r)
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case ANEG:
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opset(ANEGW, r)
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case AFMOVD:
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opset(AFMOVS, r)
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case AMOVDBR:
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@ -927,6 +941,12 @@ func buildop(ctxt *obj.Link) {
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opset(ACMPUBLE, r)
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opset(ACMPUBLT, r)
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opset(ACMPUBNE, r)
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case AMOVDEQ:
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opset(AMOVDGE, r)
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opset(AMOVDGT, r)
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opset(AMOVDLE, r)
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opset(AMOVDLT, r)
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opset(AMOVDNE, r)
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case AVL:
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opset(AVLLEZB, r)
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opset(AVLLEZH, r)
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@ -2510,22 +2530,26 @@ func addcallreloc(ctxt *obj.Link, sym *obj.LSym, add int64) *obj.Reloc {
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func branchMask(ctxt *obj.Link, p *obj.Prog) uint32 {
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switch p.As {
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case ABEQ, ACMPBEQ, ACMPUBEQ:
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case ABEQ, ACMPBEQ, ACMPUBEQ, AMOVDEQ:
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return 0x8
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case ABGE, ACMPBGE, ACMPUBGE:
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case ABGE, ACMPBGE, ACMPUBGE, AMOVDGE:
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return 0xA
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case ABGT, ACMPBGT, ACMPUBGT:
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case ABGT, ACMPBGT, ACMPUBGT, AMOVDGT:
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return 0x2
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case ABLE, ACMPBLE, ACMPUBLE:
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case ABLE, ACMPBLE, ACMPUBLE, AMOVDLE:
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return 0xC
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case ABLT, ACMPBLT, ACMPUBLT:
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case ABLT, ACMPBLT, ACMPUBLT, AMOVDLT:
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return 0x4
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case ABNE, ACMPBNE, ACMPUBNE:
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case ABNE, ACMPBNE, ACMPUBNE, AMOVDNE:
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return 0x7
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case ABLEU: // LE or unordered
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return 0xD
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case ABLTU: // LT or unordered
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return 0x5
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case ABVC:
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return 0x0 //needs extra instruction
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return 0x0 // needs extra instruction
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case ABVS:
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return 0x1
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return 0x1 // unordered
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}
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ctxt.Diag("unknown conditional branch %v", p.As)
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return 0xF
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@ -2574,9 +2598,9 @@ func asmout(ctxt *obj.Link, asm *[]byte) {
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}
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case 2: // arithmetic op reg [reg] reg
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r := int(p.Reg)
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r := p.Reg
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if r == 0 {
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r = int(p.To.Reg)
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r = p.To.Reg
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}
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var opcode uint32
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@ -2590,17 +2614,19 @@ func asmout(ctxt *obj.Link, asm *[]byte) {
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opcode = op_ALGRK
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case AADDE:
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opcode = op_ALCGR
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case AADDW:
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opcode = op_ARK
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case AMULLW:
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opcode = op_MSGFR
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case AMULLD:
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opcode = op_MSGR
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case ADIVW:
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case ADIVW, AMODW:
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opcode = op_DSGFR
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case ADIVWU:
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case ADIVWU, AMODWU:
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opcode = op_DLR
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case ADIVD:
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case ADIVD, AMODD:
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opcode = op_DSGR
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case ADIVDU:
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case ADIVDU, AMODDU:
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opcode = op_DLGR
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case AFADD:
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opcode = op_ADBR
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@ -2619,11 +2645,15 @@ func asmout(ctxt *obj.Link, asm *[]byte) {
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switch p.As {
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default:
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case AADD, AADDC:
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zRRF(opcode, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm)
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case AADD, AADDC, AADDW:
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if p.As == AADDW && r == p.To.Reg {
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zRR(op_AR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
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} else {
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zRRF(opcode, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm)
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}
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case AADDE, AMULLW, AMULLD:
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if r == int(p.To.Reg) {
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if r == p.To.Reg {
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zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm)
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} else if p.From.Reg == p.To.Reg {
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zRRE(opcode, uint32(p.To.Reg), uint32(r), asm)
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@ -2634,14 +2664,22 @@ func asmout(ctxt *obj.Link, asm *[]byte) {
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case ADIVW, ADIVWU, ADIVD, ADIVDU:
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if p.As == ADIVWU || p.As == ADIVDU {
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zRRE(op_LGR, REGTMP, REGZERO, asm)
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zRI(op_LGHI, REGTMP, 0, asm)
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}
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zRRE(op_LGR, REGTMP2, uint32(r), asm)
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zRRE(opcode, REGTMP, uint32(p.From.Reg), asm)
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zRRE(op_LGR, uint32(p.To.Reg), REGTMP2, asm)
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case AMODW, AMODWU, AMODD, AMODDU:
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if p.As == AMODWU || p.As == AMODDU {
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zRI(op_LGHI, REGTMP, 0, asm)
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}
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zRRE(op_LGR, REGTMP2, uint32(r), asm)
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zRRE(opcode, REGTMP, uint32(p.From.Reg), asm)
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zRRE(op_LGR, uint32(p.To.Reg), REGTMP, asm)
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case AFADD, AFADDS:
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if r == int(p.To.Reg) {
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if r == p.To.Reg {
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zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm)
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} else if p.From.Reg == p.To.Reg {
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zRRE(opcode, uint32(p.To.Reg), uint32(r), asm)
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@ -2651,7 +2689,7 @@ func asmout(ctxt *obj.Link, asm *[]byte) {
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}
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case AFSUB, AFSUBS, AFDIV, AFDIVS:
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if r == int(p.To.Reg) {
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if r == p.To.Reg {
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zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm)
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} else if p.From.Reg == p.To.Reg {
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zRRE(op_LGDR, REGTMP, uint32(r), asm)
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@ -2681,16 +2719,14 @@ func asmout(ctxt *obj.Link, asm *[]byte) {
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case AMOVW:
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v = int64(int32(v))
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}
|
||||
if v&0xffff == v {
|
||||
zRI(op_LLILL, uint32(p.To.Reg), uint32(v), asm)
|
||||
if int64(int16(v)) == v {
|
||||
zRI(op_LGHI, uint32(p.To.Reg), uint32(v), asm)
|
||||
} else if v&0xffff0000 == v {
|
||||
zRI(op_LLILH, uint32(p.To.Reg), uint32(v>>16), asm)
|
||||
} else if v&0xffff00000000 == v {
|
||||
zRI(op_LLIHL, uint32(p.To.Reg), uint32(v>>32), asm)
|
||||
} else if uint64(v)&0xffff000000000000 == uint64(v) {
|
||||
zRI(op_LLIHH, uint32(p.To.Reg), uint32(v>>48), asm)
|
||||
} else if int64(int16(v)) == v {
|
||||
zRI(op_LGHI, uint32(p.To.Reg), uint32(v), asm)
|
||||
} else if int64(int32(v)) == v {
|
||||
zRIL(_a, op_LGFI, uint32(p.To.Reg), uint32(v), asm)
|
||||
} else if int64(uint32(v)) == v {
|
||||
@ -2845,7 +2881,6 @@ func asmout(ctxt *obj.Link, asm *[]byte) {
|
||||
} else {
|
||||
zRRF(op_SLGRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm)
|
||||
}
|
||||
|
||||
case ASUBE:
|
||||
if r == 0 {
|
||||
r = int(p.To.Reg)
|
||||
@ -2860,6 +2895,12 @@ func asmout(ctxt *obj.Link, asm *[]byte) {
|
||||
zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm)
|
||||
zRRE(op_SLBGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
|
||||
}
|
||||
case ASUBW:
|
||||
if r == 0 {
|
||||
zRR(op_SR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
|
||||
} else {
|
||||
zRRF(op_SRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm)
|
||||
}
|
||||
}
|
||||
|
||||
case 11: // br/bl
|
||||
@ -2905,6 +2946,10 @@ func asmout(ctxt *obj.Link, asm *[]byte) {
|
||||
addrilreloc(ctxt, p.To.Sym, p.To.Offset)
|
||||
}
|
||||
|
||||
case 17: // move on condition
|
||||
m3 := branchMask(ctxt, p)
|
||||
zRRF(op_LOCGR, m3, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm)
|
||||
|
||||
case 18: // br/bl reg
|
||||
if p.As == ABL {
|
||||
zRR(op_BASR, uint32(REG_LR), uint32(p.To.Reg), asm)
|
||||
@ -2946,6 +2991,29 @@ func asmout(ctxt *obj.Link, asm *[]byte) {
|
||||
zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm)
|
||||
}
|
||||
zRIL(_a, op_ALGFI, uint32(p.To.Reg), uint32(v), asm)
|
||||
case AADDW:
|
||||
i2 := int32(v)
|
||||
if r == p.To.Reg {
|
||||
zRIL(_a, op_AFI, uint32(p.To.Reg), uint32(i2), asm)
|
||||
} else if int32(int16(i2)) == i2 {
|
||||
zRIE(_d, op_AHIK, uint32(p.To.Reg), uint32(r), uint32(i2), 0, 0, 0, 0, asm)
|
||||
} else {
|
||||
zRR(op_LR, uint32(p.To.Reg), uint32(r), asm)
|
||||
zRIL(_a, op_AFI, uint32(p.To.Reg), uint32(i2), asm)
|
||||
}
|
||||
case ASUB:
|
||||
zRIL(_a, op_LGFI, uint32(REGTMP), uint32(v), asm)
|
||||
zRRF(op_SLGRK, uint32(REGTMP), 0, uint32(p.To.Reg), uint32(r), asm)
|
||||
case ASUBC:
|
||||
if r != p.To.Reg {
|
||||
zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm)
|
||||
}
|
||||
zRIL(_a, op_SLGFI, uint32(p.To.Reg), uint32(v), asm)
|
||||
case ASUBW:
|
||||
if r != p.To.Reg {
|
||||
zRR(op_LR, uint32(p.To.Reg), uint32(r), asm)
|
||||
}
|
||||
zRIL(_a, op_SLFI, uint32(p.To.Reg), uint32(v), asm)
|
||||
case AMULLW, AMULLD:
|
||||
if r != p.To.Reg {
|
||||
zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm)
|
||||
@ -3009,19 +3077,20 @@ func asmout(ctxt *obj.Link, asm *[]byte) {
|
||||
zRRF(opcode, uint32(r), 0, uint32(p.To.Reg), REGTMP, asm)
|
||||
}
|
||||
|
||||
case 26: // mov $addr/sym reg
|
||||
case 26: // MOVD $offset(base)(index), reg
|
||||
v := regoff(ctxt, &p.From)
|
||||
r := p.From.Reg
|
||||
if r == 0 {
|
||||
r = o.param
|
||||
}
|
||||
i := p.From.Index
|
||||
if v >= 0 && v < DISP12 {
|
||||
zRX(op_LA, uint32(p.To.Reg), uint32(r), 0, uint32(v), asm)
|
||||
zRX(op_LA, uint32(p.To.Reg), uint32(r), uint32(i), uint32(v), asm)
|
||||
} else if v >= -DISP20/2 && v < DISP20/2 {
|
||||
zRXY(op_LAY, uint32(p.To.Reg), uint32(r), 0, uint32(v), asm)
|
||||
zRXY(op_LAY, uint32(p.To.Reg), uint32(r), uint32(i), uint32(v), asm)
|
||||
} else {
|
||||
zRIL(_a, op_LGFI, REGTMP, uint32(v), asm)
|
||||
zRX(op_LA, uint32(p.To.Reg), uint32(r), REGTMP, 0, asm)
|
||||
zRX(op_LA, uint32(p.To.Reg), uint32(r), REGTMP, uint32(i), asm)
|
||||
}
|
||||
|
||||
case 31: // dword
|
||||
@ -3076,6 +3145,8 @@ func asmout(ctxt *obj.Link, asm *[]byte) {
|
||||
opcode = op_LNDBR
|
||||
case AFNEG:
|
||||
opcode = op_LCDFR
|
||||
case AFNEGS:
|
||||
opcode = op_LCEBR
|
||||
case ALEDBR:
|
||||
opcode = op_LEDBR
|
||||
case ALDEBR:
|
||||
@ -3161,51 +3232,49 @@ func asmout(ctxt *obj.Link, asm *[]byte) {
|
||||
}
|
||||
|
||||
case 47: // arithmetic op (carry) reg [reg] reg
|
||||
r := p.From.Reg
|
||||
switch p.As {
|
||||
default:
|
||||
|
||||
case AADDME:
|
||||
r := int(p.From.Reg)
|
||||
if p.To.Reg == p.From.Reg {
|
||||
zRRE(op_LGR, REGTMP, uint32(p.From.Reg), asm)
|
||||
r = REGTMP
|
||||
}
|
||||
zRIL(_a, op_LGFI, uint32(p.To.Reg), 0xffffffff, asm) // p.To.Reg <- -1
|
||||
zRRE(op_ALCGR, uint32(p.To.Reg), uint32(r), asm)
|
||||
|
||||
case AADDZE:
|
||||
r := int(p.From.Reg)
|
||||
if p.To.Reg == p.From.Reg {
|
||||
zRRE(op_LGR, REGTMP, uint32(p.From.Reg), asm)
|
||||
r = REGTMP
|
||||
}
|
||||
zRRE(op_LGR, uint32(p.To.Reg), REGZERO, asm) // p.To.Reg <- 0
|
||||
zRI(op_LGHI, uint32(p.To.Reg), 0, asm)
|
||||
zRRE(op_ALCGR, uint32(p.To.Reg), uint32(r), asm)
|
||||
|
||||
case ASUBME:
|
||||
r := int(p.From.Reg)
|
||||
if p.To.Reg == p.From.Reg {
|
||||
zRRE(op_LGR, REGTMP, uint32(p.From.Reg), asm)
|
||||
r = REGTMP
|
||||
}
|
||||
zRIL(_a, op_LGFI, uint32(p.To.Reg), 0xffffffff, asm) // p.To.Reg <- -1
|
||||
zRRE(op_SLBGR, uint32(p.To.Reg), uint32(r), asm)
|
||||
|
||||
case ASUBZE:
|
||||
r := int(p.From.Reg)
|
||||
if p.To.Reg == p.From.Reg {
|
||||
zRRE(op_LGR, REGTMP, uint32(p.From.Reg), asm)
|
||||
r = REGTMP
|
||||
}
|
||||
zRRE(op_LGR, uint32(p.To.Reg), REGZERO, asm) // p.To.Reg <- 0
|
||||
zRI(op_LGHI, uint32(p.To.Reg), 0, asm)
|
||||
zRRE(op_SLBGR, uint32(p.To.Reg), uint32(r), asm)
|
||||
|
||||
case ANEG:
|
||||
r := int(p.From.Reg)
|
||||
r := p.From.Reg
|
||||
if r == 0 {
|
||||
r = int(p.To.Reg)
|
||||
r = p.To.Reg
|
||||
}
|
||||
zRRE(op_LCGR, uint32(p.To.Reg), uint32(r), asm)
|
||||
case ANEGW:
|
||||
r := p.From.Reg
|
||||
if r == 0 {
|
||||
r = p.To.Reg
|
||||
}
|
||||
zRRE(op_LCGFR, uint32(p.To.Reg), uint32(r), asm)
|
||||
}
|
||||
|
||||
case 48: // floating-point round to integer
|
||||
|
@ -109,13 +109,13 @@ func progedit(ctxt *obj.Link, p *obj.Prog) {
|
||||
// Rewrite SUB constants into ADD.
|
||||
switch p.As {
|
||||
case ASUBC:
|
||||
if p.From.Type == obj.TYPE_CONST {
|
||||
if p.From.Type == obj.TYPE_CONST && isint32(-p.From.Offset) {
|
||||
p.From.Offset = -p.From.Offset
|
||||
p.As = AADDC
|
||||
}
|
||||
|
||||
case ASUB:
|
||||
if p.From.Type == obj.TYPE_CONST {
|
||||
if p.From.Type == obj.TYPE_CONST && isint32(-p.From.Offset) {
|
||||
p.From.Offset = -p.From.Offset
|
||||
p.As = AADD
|
||||
}
|
||||
@ -258,14 +258,6 @@ func preprocess(ctxt *obj.Link, cursym *obj.LSym) {
|
||||
p.Link.Mark |= LABEL
|
||||
}
|
||||
|
||||
case ANOR:
|
||||
q = p
|
||||
if p.To.Type == obj.TYPE_REG {
|
||||
if p.To.Reg == REGZERO {
|
||||
p.Mark |= LABEL | SYNC
|
||||
}
|
||||
}
|
||||
|
||||
case ASYNC,
|
||||
AWORD:
|
||||
q = p
|
||||
@ -312,6 +304,8 @@ func preprocess(ctxt *obj.Link, cursym *obj.LSym) {
|
||||
ABGT,
|
||||
ABLE,
|
||||
ABLT,
|
||||
ABLEU,
|
||||
ABLTU,
|
||||
ABNE,
|
||||
ABR,
|
||||
ABVC,
|
||||
@ -401,7 +395,7 @@ func preprocess(ctxt *obj.Link, cursym *obj.LSym) {
|
||||
|
||||
q = p
|
||||
|
||||
if p.From3.Offset&obj.NOSPLIT == 0 {
|
||||
if p.From3.Offset&obj.NOSPLIT == 0 && p.From3.Offset&obj.NOFRAME == 0 {
|
||||
p, pPreempt = stacksplitPre(ctxt, p, autosize) // emit pre part of split check
|
||||
pPre = p
|
||||
wasSplit = true //need post part of split
|
||||
@ -440,7 +434,7 @@ func preprocess(ctxt *obj.Link, cursym *obj.LSym) {
|
||||
// if(g->panic != nil && g->panic->argp == FP) g->panic->argp = bottom-of-frame
|
||||
//
|
||||
// MOVD g_panic(g), R3
|
||||
// CMP R0, R3
|
||||
// CMP R3, $0
|
||||
// BEQ end
|
||||
// MOVD panic_argp(R3), R4
|
||||
// ADD $(autosize+8), R1, R5
|
||||
@ -466,9 +460,9 @@ func preprocess(ctxt *obj.Link, cursym *obj.LSym) {
|
||||
q = obj.Appendp(ctxt, q)
|
||||
q.As = ACMP
|
||||
q.From.Type = obj.TYPE_REG
|
||||
q.From.Reg = REG_R0
|
||||
q.To.Type = obj.TYPE_REG
|
||||
q.To.Reg = REG_R3
|
||||
q.From.Reg = REG_R3
|
||||
q.To.Type = obj.TYPE_CONST
|
||||
q.To.Offset = 0
|
||||
|
||||
q = obj.Appendp(ctxt, q)
|
||||
q.As = ABEQ
|
||||
@ -993,6 +987,7 @@ var unaryDst = map[obj.As]bool{
|
||||
ASTCKE: true,
|
||||
ASTCKF: true,
|
||||
ANEG: true,
|
||||
ANEGW: true,
|
||||
AVONE: true,
|
||||
AVZERO: true,
|
||||
}
|
||||
|
Loading…
Reference in New Issue
Block a user