mirror of
https://github.com/golang/go
synced 2024-10-05 16:41:21 -06:00
[dev.ssa] cmd/compile: add [u]int and FP to FP conversions
Change-Id: I8c17f706a3e0f1fa2d754bfb4ccd1f7a027cb3db Reviewed-on: https://go-review.googlesource.com/13744 Reviewed-by: Keith Randall <khr@golang.org>
This commit is contained in:
David Chase
parent
01490eb96c
commit
4282588694
@ -1217,6 +1217,84 @@ func (s *state) expr(n *Node) *ssa.Value {
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}
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return s.newValue1(op, n.Type, x)
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}
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var op1, op2 ssa.Op
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if ft.IsInteger() && tt.IsFloat() {
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// signed 1, 2, 4, 8, unsigned 6, 7, 9, 13
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signedSize := ft.Size()
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it := TINT32 // intermediate type in conversion, int32 or int64
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if !ft.IsSigned() {
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signedSize += 5
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}
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switch signedSize {
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case 1:
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op1 = ssa.OpSignExt8to32
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case 2:
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op1 = ssa.OpSignExt16to32
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case 4:
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op1 = ssa.OpCopy
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case 8:
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op1 = ssa.OpCopy
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it = TINT64
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case 6:
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op1 = ssa.OpZeroExt8to32
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case 7:
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op1 = ssa.OpZeroExt16to32
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case 9:
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// Go wide to dodge the unsignedness correction
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op1 = ssa.OpZeroExt32to64
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it = TINT64
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case 13:
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// unsigned 64, there is branchy correction code
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// because there is only signed-integer to FP
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// conversion in the (AMD64) instructions set.
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// Branchy correction code *may* be amenable to
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// optimization, and it can be cleanly expressed
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// in SSA, so do it here.
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if tt.Size() == 4 {
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return s.uint64Tofloat32(n, x, ft, tt)
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}
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if tt.Size() == 8 {
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return s.uint64Tofloat64(n, x, ft, tt)
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}
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default:
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s.Fatalf("weird integer to float sign extension %s -> %s", ft, tt)
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}
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if tt.Size() == 4 {
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if it == TINT64 {
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op2 = ssa.OpCvt64to32F
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} else {
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op2 = ssa.OpCvt32to32F
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}
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} else {
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if it == TINT64 {
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op2 = ssa.OpCvt64to64F
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} else {
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op2 = ssa.OpCvt32to64F
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}
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}
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if op1 == ssa.OpCopy {
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return s.newValue1(op2, n.Type, x)
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}
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return s.newValue1(op2, n.Type, s.newValue1(op1, Types[it], x))
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}
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if ft.IsFloat() && tt.IsFloat() {
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var op ssa.Op
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if ft.Size() == tt.Size() {
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op = ssa.OpCopy
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} else if ft.Size() == 4 && tt.Size() == 8 {
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op = ssa.OpCvt32Fto64F
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} else if ft.Size() == 8 && tt.Size() == 4 {
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op = ssa.OpCvt64Fto32F
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} else {
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s.Fatalf("weird float conversion %s -> %s", ft, tt)
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}
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return s.newValue1(op, n.Type, x)
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}
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// TODO: Still lack float-to-int
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s.Unimplementedf("unhandled OCONV %s -> %s", Econv(int(n.Left.Type.Etype), 0), Econv(int(n.Type.Etype), 0))
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return nil
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@ -1709,6 +1787,112 @@ func (s *state) boundsCheck(idx, len *ssa.Value) {
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s.startBlock(bNext)
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}
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type u2fcvtTab struct {
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geq, cvt2F, and, rsh, or, add ssa.Op
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one func(*state, ssa.Type, int64) *ssa.Value
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}
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var u64_f64 u2fcvtTab = u2fcvtTab{
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geq: ssa.OpGeq64,
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cvt2F: ssa.OpCvt64to64F,
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and: ssa.OpAnd64,
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rsh: ssa.OpRsh64Ux64,
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or: ssa.OpOr64,
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add: ssa.OpAdd64F,
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one: (*state).constInt64,
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}
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var u64_f32 u2fcvtTab = u2fcvtTab{
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geq: ssa.OpGeq64,
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cvt2F: ssa.OpCvt64to32F,
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and: ssa.OpAnd64,
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rsh: ssa.OpRsh64Ux64,
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or: ssa.OpOr64,
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add: ssa.OpAdd32F,
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one: (*state).constInt64,
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}
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// Excess generality on a machine with 64-bit integer registers.
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// Not used on AMD64.
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var u32_f32 u2fcvtTab = u2fcvtTab{
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geq: ssa.OpGeq32,
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cvt2F: ssa.OpCvt32to32F,
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and: ssa.OpAnd32,
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rsh: ssa.OpRsh32Ux32,
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or: ssa.OpOr32,
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add: ssa.OpAdd32F,
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one: func(s *state, t ssa.Type, x int64) *ssa.Value {
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return s.constInt32(t, int32(x))
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},
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}
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func (s *state) uint64Tofloat64(n *Node, x *ssa.Value, ft, tt *Type) *ssa.Value {
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return s.uintTofloat(&u64_f64, n, x, ft, tt)
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}
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func (s *state) uint64Tofloat32(n *Node, x *ssa.Value, ft, tt *Type) *ssa.Value {
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return s.uintTofloat(&u64_f32, n, x, ft, tt)
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}
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func (s *state) uintTofloat(cvttab *u2fcvtTab, n *Node, x *ssa.Value, ft, tt *Type) *ssa.Value {
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// if x >= 0 {
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// result = (floatY) x
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// } else {
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// y = uintX(x) ; y = x & 1
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// z = uintX(x) ; z = z >> 1
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// z = z >> 1
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// z = z | y
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// result = (floatY) z
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// z = z + z
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// }
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//
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// Code borrowed from old code generator.
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// What's going on: large 64-bit "unsigned" looks like
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// negative number to hardware's integer-to-float
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// conversion. However, because the mantissa is only
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// 63 bits, we don't need the LSB, so instead we do an
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// unsigned right shift (divide by two), convert, and
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// double. However, before we do that, we need to be
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// sure that we do not lose a "1" if that made the
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// difference in the resulting rounding. Therefore, we
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// preserve it, and OR (not ADD) it back in. The case
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// that matters is when the eleven discarded bits are
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// equal to 10000000001; that rounds up, and the 1 cannot
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// be lost else it would round down if the LSB of the
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// candidate mantissa is 0.
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cmp := s.newValue2(cvttab.geq, Types[TBOOL], x, s.zeroVal(ft))
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b := s.endBlock()
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b.Kind = ssa.BlockIf
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b.Control = cmp
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b.Likely = ssa.BranchLikely
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bThen := s.f.NewBlock(ssa.BlockPlain)
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bElse := s.f.NewBlock(ssa.BlockPlain)
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bAfter := s.f.NewBlock(ssa.BlockPlain)
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addEdge(b, bThen)
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s.startBlock(bThen)
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a0 := s.newValue1(cvttab.cvt2F, tt, x)
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s.vars[n] = a0
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s.endBlock()
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addEdge(bThen, bAfter)
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addEdge(b, bElse)
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s.startBlock(bElse)
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one := cvttab.one(s, ft, 1)
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y := s.newValue2(cvttab.and, ft, x, one)
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z := s.newValue2(cvttab.rsh, ft, x, one)
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z = s.newValue2(cvttab.or, ft, z, y)
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a := s.newValue1(cvttab.cvt2F, tt, z)
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a1 := s.newValue2(cvttab.add, tt, a, a)
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s.vars[n] = a1
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s.endBlock()
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addEdge(bElse, bAfter)
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s.startBlock(bAfter)
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return s.variable(n, n.Type)
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}
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// checkgoto checks that a goto from from to to does not
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// jump into a block or jump over variable declarations.
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// It is a copy of checkgoto in the pre-SSA backend,
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@ -2425,12 +2609,11 @@ func genValue(v *ssa.Value) {
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p.To.Scale = 4
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p.To.Index = regnum(v.Args[1])
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addAux(&p.To, v)
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case ssa.OpAMD64MOVLQSX, ssa.OpAMD64MOVWQSX, ssa.OpAMD64MOVBQSX, ssa.OpAMD64MOVLQZX, ssa.OpAMD64MOVWQZX, ssa.OpAMD64MOVBQZX:
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p := Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = regnum(v.Args[0])
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p.To.Type = obj.TYPE_REG
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p.To.Reg = regnum(v)
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case ssa.OpAMD64MOVLQSX, ssa.OpAMD64MOVWQSX, ssa.OpAMD64MOVBQSX, ssa.OpAMD64MOVLQZX, ssa.OpAMD64MOVWQZX, ssa.OpAMD64MOVBQZX,
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ssa.OpAMD64CVTSL2SS, ssa.OpAMD64CVTSL2SD, ssa.OpAMD64CVTSQ2SS, ssa.OpAMD64CVTSQ2SD,
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ssa.OpAMD64CVTSS2SL, ssa.OpAMD64CVTSD2SL, ssa.OpAMD64CVTSS2SQ, ssa.OpAMD64CVTSD2SQ,
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ssa.OpAMD64CVTSS2SD, ssa.OpAMD64CVTSD2SS:
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opregreg(v.Op.Asm(), regnum(v), regnum(v.Args[0]))
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case ssa.OpAMD64MOVXzero:
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nb := v.AuxInt
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offset := int64(0)
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140
src/cmd/compile/internal/gc/testdata/fp_ssa.go
vendored
140
src/cmd/compile/internal/gc/testdata/fp_ssa.go
vendored
@ -31,10 +31,43 @@ func fail32(s string, f func(a, b float32) float32, a, b, e float32) int {
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func expect64(s string, x, expected float64) int {
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if x != expected {
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println("Expected", expected, "for", s, ", got", x)
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return 1
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}
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return 0
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}
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func expect32(s string, x, expected float32) int {
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if x != expected {
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println("Expected", expected, "for", s, ", got", x)
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return 1
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}
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return 0
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}
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func expectAll64(s string, expected, a, b, c, d, e, f, g, h, i float64) int {
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fails := 0
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fails += expect64(s+":a", a, expected)
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fails += expect64(s+":b", b, expected)
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fails += expect64(s+":c", c, expected)
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fails += expect64(s+":d", d, expected)
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fails += expect64(s+":e", e, expected)
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fails += expect64(s+":f", f, expected)
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fails += expect64(s+":g", g, expected)
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return fails
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}
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func expectAll32(s string, expected, a, b, c, d, e, f, g, h, i float32) int {
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fails := 0
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fails += expect32(s+":a", a, expected)
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fails += expect32(s+":b", b, expected)
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fails += expect32(s+":c", c, expected)
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fails += expect32(s+":d", d, expected)
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fails += expect32(s+":e", e, expected)
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fails += expect32(s+":f", f, expected)
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fails += expect32(s+":g", g, expected)
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return fails
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}
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// manysub_ssa is designed to tickle bugs that depend on register
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// pressure or unfriendly operand ordering in registers (and at
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// least once it succeeded in this).
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@ -107,6 +140,111 @@ func div32_ssa(a, b float32) float32 {
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return a / b
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}
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func conv2Float64_ssa(a int8, b uint8, c int16, d uint16,
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e int32, f uint32, g int64, h uint64, i float32) (aa, bb, cc, dd, ee, ff, gg, hh, ii float64) {
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switch {
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}
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aa = float64(a)
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bb = float64(b)
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cc = float64(c)
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hh = float64(h)
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dd = float64(d)
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ee = float64(e)
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ff = float64(f)
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gg = float64(g)
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ii = float64(i)
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return
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}
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func conv2Float32_ssa(a int8, b uint8, c int16, d uint16,
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e int32, f uint32, g int64, h uint64, i float64) (aa, bb, cc, dd, ee, ff, gg, hh, ii float32) {
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switch {
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}
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aa = float32(a)
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bb = float32(b)
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cc = float32(c)
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dd = float32(d)
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ee = float32(e)
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ff = float32(f)
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gg = float32(g)
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hh = float32(h)
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ii = float32(i)
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return
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}
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func integer2floatConversions() int {
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fails := 0
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{
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a, b, c, d, e, f, g, h, i := conv2Float64_ssa(0, 0, 0, 0, 0, 0, 0, 0, 0)
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fails += expectAll64("zero64", 0, a, b, c, d, e, f, g, h, i)
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}
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{
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a, b, c, d, e, f, g, h, i := conv2Float64_ssa(1, 1, 1, 1, 1, 1, 1, 1, 1)
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fails += expectAll64("one64", 1, a, b, c, d, e, f, g, h, i)
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}
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{
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a, b, c, d, e, f, g, h, i := conv2Float32_ssa(0, 0, 0, 0, 0, 0, 0, 0, 0)
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fails += expectAll32("zero32", 0, a, b, c, d, e, f, g, h, i)
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}
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{
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a, b, c, d, e, f, g, h, i := conv2Float32_ssa(1, 1, 1, 1, 1, 1, 1, 1, 1)
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fails += expectAll32("one32", 1, a, b, c, d, e, f, g, h, i)
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}
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{
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// Check maximum values
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a, b, c, d, e, f, g, h, i := conv2Float64_ssa(127, 255, 32767, 65535, 0x7fffffff, 0xffffffff, 0x7fffFFFFffffFFFF, 0xffffFFFFffffFFFF, 3.402823E38)
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fails += expect64("a", a, 127)
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fails += expect64("b", b, 255)
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fails += expect64("c", c, 32767)
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fails += expect64("d", d, 65535)
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fails += expect64("e", e, float64(int32(0x7fffffff)))
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fails += expect64("f", f, float64(uint32(0xffffffff)))
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fails += expect64("g", g, float64(int64(0x7fffffffffffffff)))
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fails += expect64("h", h, float64(uint64(0xffffffffffffffff)))
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fails += expect64("i", i, float64(float32(3.402823E38)))
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}
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{
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// Check minimum values (and tweaks for unsigned)
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a, b, c, d, e, f, g, h, i := conv2Float64_ssa(-128, 254, -32768, 65534, ^0x7fffffff, 0xfffffffe, ^0x7fffFFFFffffFFFF, 0xffffFFFFffffF401, 1.5E-45)
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fails += expect64("a", a, -128)
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fails += expect64("b", b, 254)
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fails += expect64("c", c, -32768)
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fails += expect64("d", d, 65534)
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fails += expect64("e", e, float64(^int32(0x7fffffff)))
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fails += expect64("f", f, float64(uint32(0xfffffffe)))
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fails += expect64("g", g, float64(^int64(0x7fffffffffffffff)))
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fails += expect64("h", h, float64(uint64(0xfffffffffffff401)))
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fails += expect64("i", i, float64(float32(1.5E-45)))
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}
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{
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// Check maximum values
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a, b, c, d, e, f, g, h, i := conv2Float32_ssa(127, 255, 32767, 65535, 0x7fffffff, 0xffffffff, 0x7fffFFFFffffFFFF, 0xffffFFFFffffFFFF, 3.402823E38)
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fails += expect32("a", a, 127)
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fails += expect32("b", b, 255)
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fails += expect32("c", c, 32767)
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fails += expect32("d", d, 65535)
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fails += expect32("e", e, float32(int32(0x7fffffff)))
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fails += expect32("f", f, float32(uint32(0xffffffff)))
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fails += expect32("g", g, float32(int64(0x7fffffffffffffff)))
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fails += expect32("h", h, float32(uint64(0xffffffffffffffff)))
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fails += expect32("i", i, float32(float64(3.402823E38)))
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}
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{
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// Check minimum values (and tweaks for unsigned)
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a, b, c, d, e, f, g, h, i := conv2Float32_ssa(-128, 254, -32768, 65534, ^0x7fffffff, 0xfffffffe, ^0x7fffFFFFffffFFFF, 0xffffFFFFffffF401, 1.5E-45)
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fails += expect32("a", a, -128)
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fails += expect32("b", b, 254)
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fails += expect32("c", c, -32768)
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fails += expect32("d", d, 65534)
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fails += expect32("e", e, float32(^int32(0x7fffffff)))
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fails += expect32("f", f, float32(uint32(0xfffffffe)))
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fails += expect32("g", g, float32(^int64(0x7fffffffffffffff)))
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fails += expect32("h", h, float32(uint64(0xfffffffffffff401)))
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fails += expect32("i", i, float32(float64(1.5E-45)))
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}
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return fails
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}
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func main() {
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a := 3.0
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@ -157,6 +295,8 @@ func main() {
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fails += expect64("dc", dc, -9.0)
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fails += expect64("dd", dd, 44.0)
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fails += integer2floatConversions()
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if fails > 0 {
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fmt.Printf("Saw %v failures\n", fails)
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panic("Failed.")
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@ -101,6 +101,19 @@
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(ZeroExt16to64 x) -> (MOVWQZX x)
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(ZeroExt32to64 x) -> (MOVLQZX x)
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|
||||
(Cvt32to32F x) -> (CVTSL2SS x)
|
||||
(Cvt32to64F x) -> (CVTSL2SD x)
|
||||
(Cvt64to32F x) -> (CVTSQ2SS x)
|
||||
(Cvt64to64F x) -> (CVTSQ2SD x)
|
||||
|
||||
(Cvt32Fto32 x) -> (CVTSS2SL x)
|
||||
(Cvt32Fto64 x) -> (CVTSS2SQ x)
|
||||
(Cvt64Fto32 x) -> (CVTSD2SL x)
|
||||
(Cvt64Fto64 x) -> (CVTSD2SQ x)
|
||||
|
||||
(Cvt32Fto64F x) -> (CVTSS2SD x)
|
||||
(Cvt64Fto32F x) -> (CVTSD2SS x)
|
||||
|
||||
// Because we ignore high parts of registers, truncates are just copies.
|
||||
(Trunc16to8 x) -> x
|
||||
(Trunc32to8 x) -> x
|
||||
|
||||
@ -120,13 +120,14 @@ func init() {
|
||||
gpstoreconst = regInfo{inputs: []regMask{gpspsb, 0}}
|
||||
gpstoreidx = regInfo{inputs: []regMask{gpspsb, gpsp, gpsp, 0}}
|
||||
|
||||
// fp11 = regInfo{inputs: fponly, outputs: fponly}
|
||||
fp01 = regInfo{inputs: []regMask{}, outputs: fponly}
|
||||
fp21 = regInfo{inputs: []regMask{fp, fp}, outputs: fponly}
|
||||
fp21x15 = regInfo{inputs: []regMask{fp &^ x15, fp &^ x15},
|
||||
clobbers: x15, outputs: []regMask{fp &^ x15}}
|
||||
// fp2flags = regInfo{inputs: []regMask{fp, fp}, outputs: flagsonly}
|
||||
// fp1flags = regInfo{inputs: fponly, outputs: flagsonly}
|
||||
|
||||
fpgp = regInfo{inputs: fponly, outputs: gponly}
|
||||
gpfp = regInfo{inputs: gponly, outputs: fponly}
|
||||
fp11 = regInfo{inputs: fponly, outputs: fponly}
|
||||
|
||||
fpload = regInfo{inputs: []regMask{gpspsb, 0}, outputs: fponly}
|
||||
fploadidx = regInfo{inputs: []regMask{gpspsb, gpsp, 0}, outputs: fponly}
|
||||
@ -328,6 +329,17 @@ func init() {
|
||||
{name: "MOVLconst", reg: gp01, asm: "MOVL"}, // 32 low bits of auxint
|
||||
{name: "MOVQconst", reg: gp01, asm: "MOVQ"}, // auxint
|
||||
|
||||
{name: "CVTSD2SL", reg: fpgp, asm: "CVTSD2SL"}, // convert float64 to int32
|
||||
{name: "CVTSD2SQ", reg: fpgp, asm: "CVTSD2SQ"}, // convert float64 to int64
|
||||
{name: "CVTSS2SL", reg: fpgp, asm: "CVTSS2SL"}, // convert float32 to int32
|
||||
{name: "CVTSS2SQ", reg: fpgp, asm: "CVTSS2SQ"}, // convert float32 to int64
|
||||
{name: "CVTSL2SS", reg: gpfp, asm: "CVTSL2SS"}, // convert int32 to float32
|
||||
{name: "CVTSL2SD", reg: gpfp, asm: "CVTSL2SD"}, // convert int32 to float64
|
||||
{name: "CVTSQ2SS", reg: gpfp, asm: "CVTSQ2SS"}, // convert int64 to float32
|
||||
{name: "CVTSQ2SD", reg: gpfp, asm: "CVTSQ2SD"}, // convert int64 to float64
|
||||
{name: "CVTSD2SS", reg: fp11, asm: "CVTSD2SS"}, // convert float64 to float32
|
||||
{name: "CVTSS2SD", reg: fp11, asm: "CVTSS2SD"}, // convert float32 to float64
|
||||
|
||||
{name: "LEAQ", reg: gp11sb}, // arg0 + auxint + offset encoded in aux
|
||||
{name: "LEAQ1", reg: gp21sb}, // arg0 + arg1 + auxint
|
||||
{name: "LEAQ2", reg: gp21sb}, // arg0 + 2*arg1 + auxint
|
||||
|
||||
@ -287,6 +287,17 @@ var genericOps = []opData{
|
||||
{name: "Trunc64to16"},
|
||||
{name: "Trunc64to32"},
|
||||
|
||||
{name: "Cvt32to32F"},
|
||||
{name: "Cvt32to64F"},
|
||||
{name: "Cvt64to32F"},
|
||||
{name: "Cvt64to64F"},
|
||||
{name: "Cvt32Fto32"},
|
||||
{name: "Cvt32Fto64"},
|
||||
{name: "Cvt64Fto32"},
|
||||
{name: "Cvt64Fto64"},
|
||||
{name: "Cvt32Fto64F"},
|
||||
{name: "Cvt64Fto32F"},
|
||||
|
||||
// Automatically inserted safety checks
|
||||
{name: "IsNonNil"}, // arg0 != nil
|
||||
{name: "IsInBounds"}, // 0 <= arg0 < arg1
|
||||
|
||||
@ -209,6 +209,16 @@ const (
|
||||
OpAMD64MOVWconst
|
||||
OpAMD64MOVLconst
|
||||
OpAMD64MOVQconst
|
||||
OpAMD64CVTSD2SL
|
||||
OpAMD64CVTSD2SQ
|
||||
OpAMD64CVTSS2SL
|
||||
OpAMD64CVTSS2SQ
|
||||
OpAMD64CVTSL2SS
|
||||
OpAMD64CVTSL2SD
|
||||
OpAMD64CVTSQ2SS
|
||||
OpAMD64CVTSQ2SD
|
||||
OpAMD64CVTSD2SS
|
||||
OpAMD64CVTSS2SD
|
||||
OpAMD64LEAQ
|
||||
OpAMD64LEAQ1
|
||||
OpAMD64LEAQ2
|
||||
@ -441,6 +451,16 @@ const (
|
||||
OpTrunc64to8
|
||||
OpTrunc64to16
|
||||
OpTrunc64to32
|
||||
OpCvt32to32F
|
||||
OpCvt32to64F
|
||||
OpCvt64to32F
|
||||
OpCvt64to64F
|
||||
OpCvt32Fto32
|
||||
OpCvt32Fto64
|
||||
OpCvt64Fto32
|
||||
OpCvt64Fto64
|
||||
OpCvt32Fto64F
|
||||
OpCvt64Fto32F
|
||||
OpIsNonNil
|
||||
OpIsInBounds
|
||||
OpPanicNilCheck
|
||||
@ -2521,6 +2541,126 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "CVTSD2SL",
|
||||
asm: x86.ACVTSD2SL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
||||
},
|
||||
outputs: []regMask{
|
||||
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "CVTSD2SQ",
|
||||
asm: x86.ACVTSD2SQ,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
||||
},
|
||||
outputs: []regMask{
|
||||
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "CVTSS2SL",
|
||||
asm: x86.ACVTSS2SL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
||||
},
|
||||
outputs: []regMask{
|
||||
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "CVTSS2SQ",
|
||||
asm: x86.ACVTSS2SQ,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
||||
},
|
||||
outputs: []regMask{
|
||||
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "CVTSL2SS",
|
||||
asm: x86.ACVTSL2SS,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65519}, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
||||
},
|
||||
outputs: []regMask{
|
||||
4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "CVTSL2SD",
|
||||
asm: x86.ACVTSL2SD,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65519}, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
||||
},
|
||||
outputs: []regMask{
|
||||
4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "CVTSQ2SS",
|
||||
asm: x86.ACVTSQ2SS,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65519}, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
||||
},
|
||||
outputs: []regMask{
|
||||
4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "CVTSQ2SD",
|
||||
asm: x86.ACVTSQ2SD,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65519}, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
||||
},
|
||||
outputs: []regMask{
|
||||
4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "CVTSD2SS",
|
||||
asm: x86.ACVTSD2SS,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
||||
},
|
||||
outputs: []regMask{
|
||||
4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "CVTSS2SD",
|
||||
asm: x86.ACVTSS2SD,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
||||
},
|
||||
outputs: []regMask{
|
||||
4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "LEAQ",
|
||||
reg: regInfo{
|
||||
@ -3606,6 +3746,46 @@ var opcodeTable = [...]opInfo{
|
||||
name: "Trunc64to32",
|
||||
generic: true,
|
||||
},
|
||||
{
|
||||
name: "Cvt32to32F",
|
||||
generic: true,
|
||||
},
|
||||
{
|
||||
name: "Cvt32to64F",
|
||||
generic: true,
|
||||
},
|
||||
{
|
||||
name: "Cvt64to32F",
|
||||
generic: true,
|
||||
},
|
||||
{
|
||||
name: "Cvt64to64F",
|
||||
generic: true,
|
||||
},
|
||||
{
|
||||
name: "Cvt32Fto32",
|
||||
generic: true,
|
||||
},
|
||||
{
|
||||
name: "Cvt32Fto64",
|
||||
generic: true,
|
||||
},
|
||||
{
|
||||
name: "Cvt64Fto32",
|
||||
generic: true,
|
||||
},
|
||||
{
|
||||
name: "Cvt64Fto64",
|
||||
generic: true,
|
||||
},
|
||||
{
|
||||
name: "Cvt32Fto64F",
|
||||
generic: true,
|
||||
},
|
||||
{
|
||||
name: "Cvt64Fto32F",
|
||||
generic: true,
|
||||
},
|
||||
{
|
||||
name: "IsNonNil",
|
||||
generic: true,
|
||||
|
||||
@ -1688,6 +1688,166 @@ func rewriteValueAMD64(v *Value, config *Config) bool {
|
||||
goto endc395c0a53eeccf597e225a07b53047d1
|
||||
endc395c0a53eeccf597e225a07b53047d1:
|
||||
;
|
||||
case OpCvt32Fto32:
|
||||
// match: (Cvt32Fto32 x)
|
||||
// cond:
|
||||
// result: (CVTSS2SL x)
|
||||
{
|
||||
x := v.Args[0]
|
||||
v.Op = OpAMD64CVTSS2SL
|
||||
v.AuxInt = 0
|
||||
v.Aux = nil
|
||||
v.resetArgs()
|
||||
v.AddArg(x)
|
||||
return true
|
||||
}
|
||||
goto endad55e2986dea26975574ee27f4976d5e
|
||||
endad55e2986dea26975574ee27f4976d5e:
|
||||
;
|
||||
case OpCvt32Fto64:
|
||||
// match: (Cvt32Fto64 x)
|
||||
// cond:
|
||||
// result: (CVTSS2SQ x)
|
||||
{
|
||||
x := v.Args[0]
|
||||
v.Op = OpAMD64CVTSS2SQ
|
||||
v.AuxInt = 0
|
||||
v.Aux = nil
|
||||
v.resetArgs()
|
||||
v.AddArg(x)
|
||||
return true
|
||||
}
|
||||
goto end227800dc831e0b4ef80fa315133c0991
|
||||
end227800dc831e0b4ef80fa315133c0991:
|
||||
;
|
||||
case OpCvt32Fto64F:
|
||||
// match: (Cvt32Fto64F x)
|
||||
// cond:
|
||||
// result: (CVTSS2SD x)
|
||||
{
|
||||
x := v.Args[0]
|
||||
v.Op = OpAMD64CVTSS2SD
|
||||
v.AuxInt = 0
|
||||
v.Aux = nil
|
||||
v.resetArgs()
|
||||
v.AddArg(x)
|
||||
return true
|
||||
}
|
||||
goto end0bf5d6f8d182ee2b3ab7d7c2f8ff7790
|
||||
end0bf5d6f8d182ee2b3ab7d7c2f8ff7790:
|
||||
;
|
||||
case OpCvt32to32F:
|
||||
// match: (Cvt32to32F x)
|
||||
// cond:
|
||||
// result: (CVTSL2SS x)
|
||||
{
|
||||
x := v.Args[0]
|
||||
v.Op = OpAMD64CVTSL2SS
|
||||
v.AuxInt = 0
|
||||
v.Aux = nil
|
||||
v.resetArgs()
|
||||
v.AddArg(x)
|
||||
return true
|
||||
}
|
||||
goto ende0bdea2b21aecdb8399d6fd80ddc97d6
|
||||
ende0bdea2b21aecdb8399d6fd80ddc97d6:
|
||||
;
|
||||
case OpCvt32to64F:
|
||||
// match: (Cvt32to64F x)
|
||||
// cond:
|
||||
// result: (CVTSL2SD x)
|
||||
{
|
||||
x := v.Args[0]
|
||||
v.Op = OpAMD64CVTSL2SD
|
||||
v.AuxInt = 0
|
||||
v.Aux = nil
|
||||
v.resetArgs()
|
||||
v.AddArg(x)
|
||||
return true
|
||||
}
|
||||
goto ende06cbe745112bcf0e6612788ef71c958
|
||||
ende06cbe745112bcf0e6612788ef71c958:
|
||||
;
|
||||
case OpCvt64Fto32:
|
||||
// match: (Cvt64Fto32 x)
|
||||
// cond:
|
||||
// result: (CVTSD2SL x)
|
||||
{
|
||||
x := v.Args[0]
|
||||
v.Op = OpAMD64CVTSD2SL
|
||||
v.AuxInt = 0
|
||||
v.Aux = nil
|
||||
v.resetArgs()
|
||||
v.AddArg(x)
|
||||
return true
|
||||
}
|
||||
goto end1ce5fd52f29d5a42d1aa08d7ac53e49e
|
||||
end1ce5fd52f29d5a42d1aa08d7ac53e49e:
|
||||
;
|
||||
case OpCvt64Fto32F:
|
||||
// match: (Cvt64Fto32F x)
|
||||
// cond:
|
||||
// result: (CVTSD2SS x)
|
||||
{
|
||||
x := v.Args[0]
|
||||
v.Op = OpAMD64CVTSD2SS
|
||||
v.AuxInt = 0
|
||||
v.Aux = nil
|
||||
v.resetArgs()
|
||||
v.AddArg(x)
|
||||
return true
|
||||
}
|
||||
goto endfd70158a96824ced99712d606c607d94
|
||||
endfd70158a96824ced99712d606c607d94:
|
||||
;
|
||||
case OpCvt64Fto64:
|
||||
// match: (Cvt64Fto64 x)
|
||||
// cond:
|
||||
// result: (CVTSD2SQ x)
|
||||
{
|
||||
x := v.Args[0]
|
||||
v.Op = OpAMD64CVTSD2SQ
|
||||
v.AuxInt = 0
|
||||
v.Aux = nil
|
||||
v.resetArgs()
|
||||
v.AddArg(x)
|
||||
return true
|
||||
}
|
||||
goto end8239c11ce860dc3b5417d4d2ae59386a
|
||||
end8239c11ce860dc3b5417d4d2ae59386a:
|
||||
;
|
||||
case OpCvt64to32F:
|
||||
// match: (Cvt64to32F x)
|
||||
// cond:
|
||||
// result: (CVTSQ2SS x)
|
||||
{
|
||||
x := v.Args[0]
|
||||
v.Op = OpAMD64CVTSQ2SS
|
||||
v.AuxInt = 0
|
||||
v.Aux = nil
|
||||
v.resetArgs()
|
||||
v.AddArg(x)
|
||||
return true
|
||||
}
|
||||
goto endfecc08b8a8cbd2bf3be21a077c4d0d40
|
||||
endfecc08b8a8cbd2bf3be21a077c4d0d40:
|
||||
;
|
||||
case OpCvt64to64F:
|
||||
// match: (Cvt64to64F x)
|
||||
// cond:
|
||||
// result: (CVTSQ2SD x)
|
||||
{
|
||||
x := v.Args[0]
|
||||
v.Op = OpAMD64CVTSQ2SD
|
||||
v.AuxInt = 0
|
||||
v.Aux = nil
|
||||
v.resetArgs()
|
||||
v.AddArg(x)
|
||||
return true
|
||||
}
|
||||
goto endf74ce5df659f385f75c61187b515a5d0
|
||||
endf74ce5df659f385f75c61187b515a5d0:
|
||||
;
|
||||
case OpDiv16:
|
||||
// match: (Div16 x y)
|
||||
// cond:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user