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cmd/compile: optimize shift when counter has different type.

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We already handle n << (uint64(c)&63).
This change also handles n << (uint8(c)&63)
where the SSA compiler promotes the counter to 32 bits.

Fixes #19681

Change-Id: I9327d64a994286aa0dbf76eb995578880be6923a
Reviewed-on: https://go-review.googlesource.com/38550
Run-TryBot: Alexandru Moșoi <alexandru@mosoi.ro>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: Keith Randall <khr@golang.org>
This commit is contained in:
Alexandru Moșoi 2017-03-23 22:29:59 +01:00 committed by Alexandru Moșoi
parent d039d01fe9
commit 3e63cdf850
2 changed files with 55 additions and 0 deletions
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3
src/cmd/compile/internal/ssa/gen/AMD64.rules
View File

@ -635,9 +635,11 @@
(SHLL x (ANDLconst [31] y)) -> (SHLL x y)
(SHLQ x (ANDQconst [63] y)) -> (SHLQ x y)
(SHLQ x (ANDLconst [63] y)) -> (SHLQ x y)
(SHRL x (ANDLconst [31] y)) -> (SHRL x y)
(SHRQ x (ANDQconst [63] y)) -> (SHRQ x y)
(SHRQ x (ANDLconst [63] y)) -> (SHRQ x y)
// Rotate instructions
@ -1196,6 +1198,7 @@
(CMPLconst (SHRLconst _ [c]) [n]) && 0 <= n && 0 < c && c <= 32 && (1<<uint64(32-c)) <= uint64(n) -> (FlagLT_ULT)
(CMPQconst (SHRQconst _ [c]) [n]) && 0 <= n && 0 < c && c <= 64 && (1<<uint64(64-c)) <= uint64(n) -> (FlagLT_ULT)
(CMPQconst (ANDQconst _ [m]) [n]) && 0 <= m && m < n -> (FlagLT_ULT)
(CMPQconst (ANDLconst _ [m]) [n]) && 0 <= m && m < n -> (FlagLT_ULT)
(CMPLconst (ANDLconst _ [m]) [n]) && 0 <= int32(m) && int32(m) < int32(n) -> (FlagLT_ULT)
(CMPWconst (ANDLconst _ [m]) [n]) && 0 <= int16(m) && int16(m) < int16(n) -> (FlagLT_ULT)
(CMPBconst (ANDLconst _ [m]) [n]) && 0 <= int8(m) && int8(m) < int8(n) -> (FlagLT_ULT)

52
src/cmd/compile/internal/ssa/rewriteAMD64.go
View File

@ -2832,6 +2832,22 @@ func rewriteValueAMD64_OpAMD64CMPQconst(v *Value) bool {
v.reset(OpAMD64FlagLT_ULT)
return true
}
// match: (CMPQconst (ANDLconst _ [m]) [n])
// cond: 0 <= m && m < n
// result: (FlagLT_ULT)
for {
n := v.AuxInt
v_0 := v.Args[0]
if v_0.Op != OpAMD64ANDLconst {
break
}
m := v_0.AuxInt
if !(0 <= m && m < n) {
break
}
v.reset(OpAMD64FlagLT_ULT)
return true
}
// match: (CMPQconst (ANDQ x y) [0])
// cond:
// result: (TESTQ x y)
@ -15680,6 +15696,24 @@ func rewriteValueAMD64_OpAMD64SHLQ(v *Value) bool {
v.AddArg(y)
return true
}
// match: (SHLQ x (ANDLconst [63] y))
// cond:
// result: (SHLQ x y)
for {
x := v.Args[0]
v_1 := v.Args[1]
if v_1.Op != OpAMD64ANDLconst {
break
}
if v_1.AuxInt != 63 {
break
}
y := v_1.Args[0]
v.reset(OpAMD64SHLQ)
v.AddArg(x)
v.AddArg(y)
return true
}
return false
}
func rewriteValueAMD64_OpAMD64SHLQconst(v *Value) bool {
@ -15901,6 +15935,24 @@ func rewriteValueAMD64_OpAMD64SHRQ(v *Value) bool {
v.AddArg(y)
return true
}
// match: (SHRQ x (ANDLconst [63] y))
// cond:
// result: (SHRQ x y)
for {
x := v.Args[0]
v_1 := v.Args[1]
if v_1.Op != OpAMD64ANDLconst {
break
}
if v_1.AuxInt != 63 {
break
}
y := v_1.Args[0]
v.reset(OpAMD64SHRQ)
v.AddArg(x)
v.AddArg(y)
return true
}
return false
}
func rewriteValueAMD64_OpAMD64SHRQconst(v *Value) bool {