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cmd/compile: add PPC64 ssa ops to support carry chain arithmetic
These are the opcodes required to lower math/bits.Add64 and math/bits.Sub64 directly into ssa form. Likewise, opcodes which clobber CA are marked. This does not alter code generation. It prepares for future changes to support scheduling carry chaining ops more effectively, and then changes to lower into PPC64 opcodes. Change-Id: I2723deee4a98b3c365f691857512df53280ae40f Reviewed-on: https://go-review.googlesource.com/c/go/+/394594 Trust: Keith Randall <khr@golang.org> Run-TryBot: Paul Murphy <murp@ibm.com> TryBot-Result: Gopher Robot <gobot@golang.org> Reviewed-by: Cherry Mui <cherryyz@google.com>
This commit is contained in:
Paul E. Murphy
Paul Murphy
parent
dac0220841
commit
3d7ca9f7c0
@ -733,6 +733,41 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
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p.To.Type = obj.TYPE_REG
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p.To.Reg = v.Reg()
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case ssa.OpPPC64ADDC, ssa.OpPPC64ADDE, ssa.OpPPC64SUBC, ssa.OpPPC64SUBE:
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r := v.Reg0() // CA is the first, implied argument.
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r1 := v.Args[0].Reg()
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r2 := v.Args[1].Reg()
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p := s.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = r2
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p.Reg = r1
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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case ssa.OpPPC64ADDZEzero, ssa.OpPPC64SUBZEzero:
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p := s.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = ppc64.REG_R0
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p.To.Type = obj.TYPE_REG
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p.To.Reg = v.Reg()
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case ssa.OpPPC64ADDCconst:
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p := s.Prog(v.Op.Asm())
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p.Reg = v.Args[0].Reg()
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p.From.Type = obj.TYPE_CONST
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p.From.Offset = v.AuxInt
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p.To.Type = obj.TYPE_REG
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// Output is a pair, the second is the CA, which is implied.
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p.To.Reg = v.Reg0()
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case ssa.OpPPC64SUBCconst:
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p := s.Prog(v.Op.Asm())
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p.SetFrom3Const(v.AuxInt)
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p.From.Type = obj.TYPE_REG
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p.From.Reg = v.Args[0].Reg()
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p.To.Type = obj.TYPE_REG
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p.To.Reg = v.Reg0()
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case ssa.OpPPC64SUBFCconst:
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p := s.Prog(v.Op.Asm())
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p.SetFrom3Const(v.AuxInt)
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@ -139,10 +139,14 @@ func init() {
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// tls = buildReg("R13")
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gp01 = regInfo{inputs: nil, outputs: []regMask{gp}}
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gp11 = regInfo{inputs: []regMask{gp | sp | sb}, outputs: []regMask{gp}}
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xergp = regInfo{inputs: []regMask{xer}, outputs: []regMask{gp}, clobbers: xer}
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gp11cxer = regInfo{inputs: []regMask{gp | sp | sb}, outputs: []regMask{gp}, clobbers: xer}
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gp11xer = regInfo{inputs: []regMask{gp | sp | sb}, outputs: []regMask{gp, xer}}
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gp21 = regInfo{inputs: []regMask{gp | sp | sb, gp | sp | sb}, outputs: []regMask{gp}}
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gp21a0 = regInfo{inputs: []regMask{gp, gp | sp | sb}, outputs: []regMask{gp}}
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gp21cxer = regInfo{inputs: []regMask{gp | sp | sb, gp | sp | sb}, outputs: []regMask{gp}, clobbers: xer}
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gp21xer = regInfo{inputs: []regMask{gp | sp | sb, gp | sp | sb}, outputs: []regMask{gp, xer}, clobbers: xer}
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gp2xer1xer = regInfo{inputs: []regMask{gp | sp | sb, gp | sp | sb, xer}, outputs: []regMask{gp, xer}, clobbers: xer}
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gp31 = regInfo{inputs: []regMask{gp | sp | sb, gp | sp | sb, gp | sp | sb}, outputs: []regMask{gp}}
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gp22 = regInfo{inputs: []regMask{gp | sp | sb, gp | sp | sb}, outputs: []regMask{gp, gp}}
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gp32 = regInfo{inputs: []regMask{gp | sp | sb, gp | sp | sb, gp | sp | sb}, outputs: []regMask{gp, gp}}
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@ -223,6 +227,16 @@ func init() {
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{name: "LoweredAdd64Carry", argLength: 3, reg: gp32, resultNotInArgs: true}, // arg0 + arg1 + carry, returns (sum, carry)
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// Operations which consume or generate the CA (xer)
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{name: "ADDC", argLength: 2, reg: gp21xer, asm: "ADDC", commutative: true, typ: "(UInt64, UInt64)"}, // arg0 + arg1 -> out, CA
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{name: "SUBC", argLength: 2, reg: gp21xer, asm: "SUBC", typ: "(UInt64, UInt64)"}, // arg0 - arg1 -> out, CA
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{name: "ADDCconst", argLength: 1, reg: gp11xer, asm: "ADDC", typ: "(UInt64, UInt64)", aux: "Int64"}, // arg0 + imm16 -> out, CA
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{name: "SUBCconst", argLength: 1, reg: gp11xer, asm: "SUBC", typ: "(UInt64, UInt64)", aux: "Int64"}, // imm16 - arg0 -> out, CA
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{name: "ADDE", argLength: 3, reg: gp2xer1xer, asm: "ADDE", typ: "(UInt64, UInt64)", commutative: true}, // arg0 + arg1 + CA (arg2) -> out, CA
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{name: "SUBE", argLength: 3, reg: gp2xer1xer, asm: "SUBE", typ: "(UInt64, UInt64)"}, // arg0 - arg1 - CA (arg2) -> out, CA
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{name: "ADDZEzero", argLength: 1, reg: xergp, asm: "ADDZE", typ: "UInt64"}, // CA (arg0) + $0 -> out
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{name: "SUBZEzero", argLength: 1, reg: xergp, asm: "SUBZE", typ: "UInt64"}, // $0 - CA (arg0) -> out
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{name: "SRADconst", argLength: 1, reg: gp11cxer, asm: "SRAD", aux: "Int64"}, // signed arg0 >> auxInt, 0 <= auxInt < 64, 64 bit width
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{name: "SRAWconst", argLength: 1, reg: gp11cxer, asm: "SRAW", aux: "Int64"}, // signed arg0 >> auxInt, 0 <= auxInt < 32, 32 bit width
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{name: "SRDconst", argLength: 1, reg: gp11, asm: "SRD", aux: "Int64"}, // unsigned arg0 >> auxInt, 0 <= auxInt < 64, 64 bit width
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@ -1911,6 +1911,14 @@ const (
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OpPPC64CLRLSLWI
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OpPPC64CLRLSLDI
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OpPPC64LoweredAdd64Carry
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OpPPC64ADDC
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OpPPC64SUBC
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OpPPC64ADDCconst
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OpPPC64SUBCconst
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OpPPC64ADDE
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OpPPC64SUBE
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OpPPC64ADDZEzero
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OpPPC64SUBZEzero
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OpPPC64SRADconst
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OpPPC64SRAWconst
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OpPPC64SRDconst
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@ -25578,6 +25586,132 @@ var opcodeTable = [...]opInfo{
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},
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},
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},
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{
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name: "ADDC",
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argLen: 2,
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commutative: true,
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asm: ppc64.AADDC,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
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{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
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},
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clobbers: 9223372036854775808, // XER
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outputs: []outputInfo{
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{1, 9223372036854775808}, // XER
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{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
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},
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},
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},
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{
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name: "SUBC",
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argLen: 2,
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asm: ppc64.ASUBC,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
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{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
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},
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clobbers: 9223372036854775808, // XER
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outputs: []outputInfo{
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{1, 9223372036854775808}, // XER
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{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
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},
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},
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},
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{
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name: "ADDCconst",
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auxType: auxInt64,
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argLen: 1,
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asm: ppc64.AADDC,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
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},
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outputs: []outputInfo{
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{1, 9223372036854775808}, // XER
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{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
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},
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},
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},
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{
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name: "SUBCconst",
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auxType: auxInt64,
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argLen: 1,
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asm: ppc64.ASUBC,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
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},
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outputs: []outputInfo{
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{1, 9223372036854775808}, // XER
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{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
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},
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},
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},
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{
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name: "ADDE",
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argLen: 3,
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commutative: true,
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asm: ppc64.AADDE,
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reg: regInfo{
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inputs: []inputInfo{
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{2, 9223372036854775808}, // XER
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{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
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{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
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},
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clobbers: 9223372036854775808, // XER
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outputs: []outputInfo{
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{1, 9223372036854775808}, // XER
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{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
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},
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},
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},
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{
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name: "SUBE",
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argLen: 3,
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asm: ppc64.ASUBE,
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reg: regInfo{
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inputs: []inputInfo{
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{2, 9223372036854775808}, // XER
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{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
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{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
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},
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clobbers: 9223372036854775808, // XER
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outputs: []outputInfo{
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{1, 9223372036854775808}, // XER
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{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
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},
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},
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},
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{
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name: "ADDZEzero",
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argLen: 1,
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asm: ppc64.AADDZE,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 9223372036854775808}, // XER
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},
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clobbers: 9223372036854775808, // XER
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outputs: []outputInfo{
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{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
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},
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},
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},
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{
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name: "SUBZEzero",
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argLen: 1,
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asm: ppc64.ASUBZE,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 9223372036854775808}, // XER
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},
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clobbers: 9223372036854775808, // XER
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outputs: []outputInfo{
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{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
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},
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},
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},
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{
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name: "SRADconst",
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auxType: auxInt64,
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