From 3ca3ca51d70aac890fb023786db1fcbbeea139f1 Mon Sep 17 00:00:00 2001 From: Constantin Konstantinidis Date: Thu, 24 Sep 2020 21:44:32 +0200 Subject: [PATCH] cmd/compile: enforce strongly typed rules for ARM (to32) Type casting changed to 32 from 64. L1055-L1056 L1193-L1194, L1197-L1198 toolstash-check successful. Change-Id: Icdb9985673292294bc4549afaaa6cf4fcf92ffa8 Reviewed-on: https://go-review.googlesource.com/c/go/+/257640 Trust: Josh Bleecher Snyder Reviewed-by: Keith Randall --- src/cmd/compile/internal/ssa/gen/ARM.rules | 12 +++--- src/cmd/compile/internal/ssa/rewriteARM.go | 48 +++++++++++----------- 2 files changed, 30 insertions(+), 30 deletions(-) diff --git a/src/cmd/compile/internal/ssa/gen/ARM.rules b/src/cmd/compile/internal/ssa/gen/ARM.rules index aad7236d598..cfedde5d5e8 100644 --- a/src/cmd/compile/internal/ssa/gen/ARM.rules +++ b/src/cmd/compile/internal/ssa/gen/ARM.rules @@ -1052,8 +1052,8 @@ (BICshiftRL x (MOVWconst [c]) [d]) => (BICconst x [int32(uint32(c)>>uint64(d))]) (BICshiftRA x (MOVWconst [c]) [d]) => (BICconst x [c>>uint64(d)]) (MVNshiftLL (MOVWconst [c]) [d]) => (MOVWconst [^(c< (MOVWconst [^int64(uint32(c)>>uint64(d))]) -(MVNshiftRA (MOVWconst [c]) [d]) -> (MOVWconst [^int64(int32(c)>>uint64(d))]) +(MVNshiftRL (MOVWconst [c]) [d]) => (MOVWconst [^int32(uint32(c)>>uint64(d))]) +(MVNshiftRA (MOVWconst [c]) [d]) => (MOVWconst [int32(c)>>uint64(d)]) (CMPshiftLL x (MOVWconst [c]) [d]) => (CMPconst x [c< (CMPconst x [int32(uint32(c)>>uint64(d))]) (CMPshiftRA x (MOVWconst [c]) [d]) => (CMPconst x [c>>uint64(d)]) @@ -1190,12 +1190,12 @@ (MOVWstoreidx ptr (SRAconst idx [c]) val mem) => (MOVWstoreshiftRA ptr idx [c] val mem) (MOVWstoreidx (SRAconst idx [c]) ptr val mem) => (MOVWstoreshiftRA ptr idx [c] val mem) -(MOVWloadshiftLL ptr (MOVWconst [c]) [d] mem) -> (MOVWload [int64(uint32(c)< (MOVWload [int64(uint32(c)>>uint64(d))] ptr mem) +(MOVWloadshiftLL ptr (MOVWconst [c]) [d] mem) => (MOVWload [int32(uint32(c)< (MOVWload [int32(uint32(c)>>uint64(d))] ptr mem) (MOVWloadshiftRA ptr (MOVWconst [c]) [d] mem) => (MOVWload [c>>uint64(d)] ptr mem) -(MOVWstoreshiftLL ptr (MOVWconst [c]) [d] val mem) -> (MOVWstore [int64(uint32(c)< (MOVWstore [int64(uint32(c)>>uint64(d))] ptr val mem) +(MOVWstoreshiftLL ptr (MOVWconst [c]) [d] val mem) => (MOVWstore [int32(uint32(c)< (MOVWstore [int32(uint32(c)>>uint64(d))] ptr val mem) (MOVWstoreshiftRA ptr (MOVWconst [c]) [d] val mem) => (MOVWstore [c>>uint64(d)] ptr val mem) // generic simplifications diff --git a/src/cmd/compile/internal/ssa/rewriteARM.go b/src/cmd/compile/internal/ssa/rewriteARM.go index 435da688b77..eff01927dfc 100644 --- a/src/cmd/compile/internal/ssa/rewriteARM.go +++ b/src/cmd/compile/internal/ssa/rewriteARM.go @@ -6412,17 +6412,17 @@ func rewriteValueARM_OpARMMOVWloadshiftLL(v *Value) bool { return true } // match: (MOVWloadshiftLL ptr (MOVWconst [c]) [d] mem) - // result: (MOVWload [int64(uint32(c)<>uint64(d))] ptr mem) + // result: (MOVWload [int32(uint32(c)>>uint64(d))] ptr mem) for { - d := v.AuxInt + d := auxIntToInt32(v.AuxInt) ptr := v_0 if v_1.Op != OpARMMOVWconst { break } - c := v_1.AuxInt + c := auxIntToInt32(v_1.AuxInt) mem := v_2 v.reset(OpARMMOVWload) - v.AuxInt = int64(uint32(c) >> uint64(d)) + v.AuxInt = int32ToAuxInt(int32(uint32(c) >> uint64(d))) v.AddArg2(ptr, mem) return true } @@ -6833,18 +6833,18 @@ func rewriteValueARM_OpARMMOVWstoreshiftLL(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (MOVWstoreshiftLL ptr (MOVWconst [c]) [d] val mem) - // result: (MOVWstore [int64(uint32(c)<>uint64(d))] ptr val mem) + // result: (MOVWstore [int32(uint32(c)>>uint64(d))] ptr val mem) for { - d := v.AuxInt + d := auxIntToInt32(v.AuxInt) ptr := v_0 if v_1.Op != OpARMMOVWconst { break } - c := v_1.AuxInt + c := auxIntToInt32(v_1.AuxInt) val := v_2 mem := v_3 v.reset(OpARMMOVWstore) - v.AuxInt = int64(uint32(c) >> uint64(d)) + v.AuxInt = int32ToAuxInt(int32(uint32(c) >> uint64(d))) v.AddArg3(ptr, val, mem) return true } @@ -8105,15 +8105,15 @@ func rewriteValueARM_OpARMMVNshiftLLreg(v *Value) bool { func rewriteValueARM_OpARMMVNshiftRA(v *Value) bool { v_0 := v.Args[0] // match: (MVNshiftRA (MOVWconst [c]) [d]) - // result: (MOVWconst [^int64(int32(c)>>uint64(d))]) + // result: (MOVWconst [int32(c)>>uint64(d)]) for { - d := v.AuxInt + d := auxIntToInt32(v.AuxInt) if v_0.Op != OpARMMOVWconst { break } - c := v_0.AuxInt + c := auxIntToInt32(v_0.AuxInt) v.reset(OpARMMOVWconst) - v.AuxInt = ^int64(int32(c) >> uint64(d)) + v.AuxInt = int32ToAuxInt(int32(c) >> uint64(d)) return true } return false @@ -8139,15 +8139,15 @@ func rewriteValueARM_OpARMMVNshiftRAreg(v *Value) bool { func rewriteValueARM_OpARMMVNshiftRL(v *Value) bool { v_0 := v.Args[0] // match: (MVNshiftRL (MOVWconst [c]) [d]) - // result: (MOVWconst [^int64(uint32(c)>>uint64(d))]) + // result: (MOVWconst [^int32(uint32(c)>>uint64(d))]) for { - d := v.AuxInt + d := auxIntToInt32(v.AuxInt) if v_0.Op != OpARMMOVWconst { break } - c := v_0.AuxInt + c := auxIntToInt32(v_0.AuxInt) v.reset(OpARMMOVWconst) - v.AuxInt = ^int64(uint32(c) >> uint64(d)) + v.AuxInt = int32ToAuxInt(^int32(uint32(c) >> uint64(d))) return true } return false