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cmd/compile: enforce strongly typed rules for ARM (to32)

Type casting changed to 32 from 64.
L1055-L1056
L1193-L1194, L1197-L1198

toolstash-check successful.

Change-Id: Icdb9985673292294bc4549afaaa6cf4fcf92ffa8
Reviewed-on: https://go-review.googlesource.com/c/go/+/257640
Trust: Josh Bleecher Snyder <josharian@gmail.com>
Reviewed-by: Keith Randall <khr@golang.org>
This commit is contained in:
Constantin Konstantinidis 2020-09-24 21:44:32 +02:00 committed by Keith Randall
parent b7a2d413a3
commit 3ca3ca51d7
2 changed files with 30 additions and 30 deletions

View File

@ -1052,8 +1052,8 @@
(BICshiftRL x (MOVWconst [c]) [d]) => (BICconst x [int32(uint32(c)>>uint64(d))])
(BICshiftRA x (MOVWconst [c]) [d]) => (BICconst x [c>>uint64(d)])
(MVNshiftLL (MOVWconst [c]) [d]) => (MOVWconst [^(c<<uint64(d))])
(MVNshiftRL (MOVWconst [c]) [d]) -> (MOVWconst [^int64(uint32(c)>>uint64(d))])
(MVNshiftRA (MOVWconst [c]) [d]) -> (MOVWconst [^int64(int32(c)>>uint64(d))])
(MVNshiftRL (MOVWconst [c]) [d]) => (MOVWconst [^int32(uint32(c)>>uint64(d))])
(MVNshiftRA (MOVWconst [c]) [d]) => (MOVWconst [int32(c)>>uint64(d)])
(CMPshiftLL x (MOVWconst [c]) [d]) => (CMPconst x [c<<uint64(d)])
(CMPshiftRL x (MOVWconst [c]) [d]) => (CMPconst x [int32(uint32(c)>>uint64(d))])
(CMPshiftRA x (MOVWconst [c]) [d]) => (CMPconst x [c>>uint64(d)])
@ -1190,12 +1190,12 @@
(MOVWstoreidx ptr (SRAconst idx [c]) val mem) => (MOVWstoreshiftRA ptr idx [c] val mem)
(MOVWstoreidx (SRAconst idx [c]) ptr val mem) => (MOVWstoreshiftRA ptr idx [c] val mem)
(MOVWloadshiftLL ptr (MOVWconst [c]) [d] mem) -> (MOVWload [int64(uint32(c)<<uint64(d))] ptr mem)
(MOVWloadshiftRL ptr (MOVWconst [c]) [d] mem) -> (MOVWload [int64(uint32(c)>>uint64(d))] ptr mem)
(MOVWloadshiftLL ptr (MOVWconst [c]) [d] mem) => (MOVWload [int32(uint32(c)<<uint64(d))] ptr mem)
(MOVWloadshiftRL ptr (MOVWconst [c]) [d] mem) => (MOVWload [int32(uint32(c)>>uint64(d))] ptr mem)
(MOVWloadshiftRA ptr (MOVWconst [c]) [d] mem) => (MOVWload [c>>uint64(d)] ptr mem)
(MOVWstoreshiftLL ptr (MOVWconst [c]) [d] val mem) -> (MOVWstore [int64(uint32(c)<<uint64(d))] ptr val mem)
(MOVWstoreshiftRL ptr (MOVWconst [c]) [d] val mem) -> (MOVWstore [int64(uint32(c)>>uint64(d))] ptr val mem)
(MOVWstoreshiftLL ptr (MOVWconst [c]) [d] val mem) => (MOVWstore [int32(uint32(c)<<uint64(d))] ptr val mem)
(MOVWstoreshiftRL ptr (MOVWconst [c]) [d] val mem) => (MOVWstore [int32(uint32(c)>>uint64(d))] ptr val mem)
(MOVWstoreshiftRA ptr (MOVWconst [c]) [d] val mem) => (MOVWstore [c>>uint64(d)] ptr val mem)
// generic simplifications

View File

@ -6412,17 +6412,17 @@ func rewriteValueARM_OpARMMOVWloadshiftLL(v *Value) bool {
return true
}
// match: (MOVWloadshiftLL ptr (MOVWconst [c]) [d] mem)
// result: (MOVWload [int64(uint32(c)<<uint64(d))] ptr mem)
// result: (MOVWload [int32(uint32(c)<<uint64(d))] ptr mem)
for {
d := v.AuxInt
d := auxIntToInt32(v.AuxInt)
ptr := v_0
if v_1.Op != OpARMMOVWconst {
break
}
c := v_1.AuxInt
c := auxIntToInt32(v_1.AuxInt)
mem := v_2
v.reset(OpARMMOVWload)
v.AuxInt = int64(uint32(c) << uint64(d))
v.AuxInt = int32ToAuxInt(int32(uint32(c) << uint64(d)))
v.AddArg2(ptr, mem)
return true
}
@ -6492,17 +6492,17 @@ func rewriteValueARM_OpARMMOVWloadshiftRL(v *Value) bool {
return true
}
// match: (MOVWloadshiftRL ptr (MOVWconst [c]) [d] mem)
// result: (MOVWload [int64(uint32(c)>>uint64(d))] ptr mem)
// result: (MOVWload [int32(uint32(c)>>uint64(d))] ptr mem)
for {
d := v.AuxInt
d := auxIntToInt32(v.AuxInt)
ptr := v_0
if v_1.Op != OpARMMOVWconst {
break
}
c := v_1.AuxInt
c := auxIntToInt32(v_1.AuxInt)
mem := v_2
v.reset(OpARMMOVWload)
v.AuxInt = int64(uint32(c) >> uint64(d))
v.AuxInt = int32ToAuxInt(int32(uint32(c) >> uint64(d)))
v.AddArg2(ptr, mem)
return true
}
@ -6833,18 +6833,18 @@ func rewriteValueARM_OpARMMOVWstoreshiftLL(v *Value) bool {
v_1 := v.Args[1]
v_0 := v.Args[0]
// match: (MOVWstoreshiftLL ptr (MOVWconst [c]) [d] val mem)
// result: (MOVWstore [int64(uint32(c)<<uint64(d))] ptr val mem)
// result: (MOVWstore [int32(uint32(c)<<uint64(d))] ptr val mem)
for {
d := v.AuxInt
d := auxIntToInt32(v.AuxInt)
ptr := v_0
if v_1.Op != OpARMMOVWconst {
break
}
c := v_1.AuxInt
c := auxIntToInt32(v_1.AuxInt)
val := v_2
mem := v_3
v.reset(OpARMMOVWstore)
v.AuxInt = int64(uint32(c) << uint64(d))
v.AuxInt = int32ToAuxInt(int32(uint32(c) << uint64(d)))
v.AddArg3(ptr, val, mem)
return true
}
@ -6879,18 +6879,18 @@ func rewriteValueARM_OpARMMOVWstoreshiftRL(v *Value) bool {
v_1 := v.Args[1]
v_0 := v.Args[0]
// match: (MOVWstoreshiftRL ptr (MOVWconst [c]) [d] val mem)
// result: (MOVWstore [int64(uint32(c)>>uint64(d))] ptr val mem)
// result: (MOVWstore [int32(uint32(c)>>uint64(d))] ptr val mem)
for {
d := v.AuxInt
d := auxIntToInt32(v.AuxInt)
ptr := v_0
if v_1.Op != OpARMMOVWconst {
break
}
c := v_1.AuxInt
c := auxIntToInt32(v_1.AuxInt)
val := v_2
mem := v_3
v.reset(OpARMMOVWstore)
v.AuxInt = int64(uint32(c) >> uint64(d))
v.AuxInt = int32ToAuxInt(int32(uint32(c) >> uint64(d)))
v.AddArg3(ptr, val, mem)
return true
}
@ -8105,15 +8105,15 @@ func rewriteValueARM_OpARMMVNshiftLLreg(v *Value) bool {
func rewriteValueARM_OpARMMVNshiftRA(v *Value) bool {
v_0 := v.Args[0]
// match: (MVNshiftRA (MOVWconst [c]) [d])
// result: (MOVWconst [^int64(int32(c)>>uint64(d))])
// result: (MOVWconst [int32(c)>>uint64(d)])
for {
d := v.AuxInt
d := auxIntToInt32(v.AuxInt)
if v_0.Op != OpARMMOVWconst {
break
}
c := v_0.AuxInt
c := auxIntToInt32(v_0.AuxInt)
v.reset(OpARMMOVWconst)
v.AuxInt = ^int64(int32(c) >> uint64(d))
v.AuxInt = int32ToAuxInt(int32(c) >> uint64(d))
return true
}
return false
@ -8139,15 +8139,15 @@ func rewriteValueARM_OpARMMVNshiftRAreg(v *Value) bool {
func rewriteValueARM_OpARMMVNshiftRL(v *Value) bool {
v_0 := v.Args[0]
// match: (MVNshiftRL (MOVWconst [c]) [d])
// result: (MOVWconst [^int64(uint32(c)>>uint64(d))])
// result: (MOVWconst [^int32(uint32(c)>>uint64(d))])
for {
d := v.AuxInt
d := auxIntToInt32(v.AuxInt)
if v_0.Op != OpARMMOVWconst {
break
}
c := v_0.AuxInt
c := auxIntToInt32(v_0.AuxInt)
v.reset(OpARMMOVWconst)
v.AuxInt = ^int64(uint32(c) >> uint64(d))
v.AuxInt = int32ToAuxInt(^int32(uint32(c) >> uint64(d)))
return true
}
return false