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https://github.com/golang/go
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cmd/compile: simplify div/mod on ARM
On ARM, DIV, DIVU, MOD, MODU are pseudo instructions that makes runtime calls _div/_udiv/_mod/_umod, which themselves are wrappers of udiv. The udiv function does the real thing. Instead of generating these pseudo instructions, call to udiv directly. This removes one layer of wrappers (which has an awkward way of passing argument), and also allows combining DIV and MOD if both results are needed. Change-Id: I118afc3986db3a1daabb5c1e6e57430888c91817 Reviewed-on: https://go-review.googlesource.com/29390 Reviewed-by: David Chase <drchase@google.com>
This commit is contained in:
Cherry Zhang
parent
f964810025
commit
38cd79889e
@ -196,21 +196,11 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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} else {
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p.To.Name = obj.NAME_AUTO
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}
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case ssa.OpARMDIV,
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ssa.OpARMDIVU,
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ssa.OpARMMOD,
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ssa.OpARMMODU:
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// Note: for software division the assembler rewrite these
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// instructions to sequence of instructions:
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// - it puts numerator in R11 and denominator in g.m.divmod
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// and call (say) _udiv
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// - _udiv saves R0-R3 on stack and call udiv, restores R0-R3
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// before return
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// - udiv does the actual work
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//TODO: set approperiate regmasks and call udiv directly?
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// need to be careful for negative case
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// Or, as soft div is already expensive, we don't care?
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fallthrough
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case ssa.OpARMUDIVrtcall:
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p := gc.Prog(obj.ACALL)
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p.To.Type = obj.TYPE_MEM
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p.To.Name = obj.NAME_EXTERN
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p.To.Sym = obj.Linklookup(gc.Ctxt, "udiv", 0)
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case ssa.OpARMADD,
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ssa.OpARMADC,
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ssa.OpARMSUB,
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@ -230,12 +230,8 @@ func NewConfig(arch string, fe Frontend, ctxt *obj.Link, optimize bool) *Config
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if c.nacl {
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c.noDuffDevice = true // Don't use Duff's device on NaCl
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// ARM assembler rewrites DIV/MOD to runtime calls, which
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// clobber R12 on nacl
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opcodeTable[OpARMDIV].reg.clobbers |= 1 << 12 // R12
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opcodeTable[OpARMDIVU].reg.clobbers |= 1 << 12 // R12
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opcodeTable[OpARMMOD].reg.clobbers |= 1 << 12 // R12
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opcodeTable[OpARMMODU].reg.clobbers |= 1 << 12 // R12
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// runtime call clobber R12 on nacl
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opcodeTable[OpARMUDIVrtcall].reg.clobbers |= 1 << 12 // R12
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}
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// Assign IDs to preallocated values/blocks.
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@ -37,21 +37,31 @@
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(Mul32uhilo x y) -> (MULLU x y)
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(Div32 x y) -> (DIV x y)
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(Div32u x y) -> (DIVU x y)
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(Div16 x y) -> (DIV (SignExt16to32 x) (SignExt16to32 y))
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(Div16u x y) -> (DIVU (ZeroExt16to32 x) (ZeroExt16to32 y))
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(Div8 x y) -> (DIV (SignExt8to32 x) (SignExt8to32 y))
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(Div8u x y) -> (DIVU (ZeroExt8to32 x) (ZeroExt8to32 y))
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(Div32 x y) ->
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(SUB (XOR <config.fe.TypeUInt32()> // negate the result if one operand is negative
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(Select0 <config.fe.TypeUInt32()> (UDIVrtcall
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(SUB <config.fe.TypeUInt32()> (XOR x <config.fe.TypeUInt32()> (Signmask x)) (Signmask x)) // negate x if negative
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(SUB <config.fe.TypeUInt32()> (XOR y <config.fe.TypeUInt32()> (Signmask y)) (Signmask y)))) // negate y if negative
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(Signmask (XOR <config.fe.TypeUInt32()> x y))) (Signmask (XOR <config.fe.TypeUInt32()> x y)))
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(Div32u x y) -> (Select0 <config.fe.TypeUInt32()> (UDIVrtcall x y))
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(Div16 x y) -> (Div32 (SignExt16to32 x) (SignExt16to32 y))
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(Div16u x y) -> (Div32u (ZeroExt16to32 x) (ZeroExt16to32 y))
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(Div8 x y) -> (Div32 (SignExt8to32 x) (SignExt8to32 y))
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(Div8u x y) -> (Div32u (ZeroExt8to32 x) (ZeroExt8to32 y))
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(Div32F x y) -> (DIVF x y)
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(Div64F x y) -> (DIVD x y)
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(Mod32 x y) -> (MOD x y)
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(Mod32u x y) -> (MODU x y)
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(Mod16 x y) -> (MOD (SignExt16to32 x) (SignExt16to32 y))
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(Mod16u x y) -> (MODU (ZeroExt16to32 x) (ZeroExt16to32 y))
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(Mod8 x y) -> (MOD (SignExt8to32 x) (SignExt8to32 y))
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(Mod8u x y) -> (MODU (ZeroExt8to32 x) (ZeroExt8to32 y))
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(Mod32 x y) ->
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(SUB (XOR <config.fe.TypeUInt32()> // negate the result if x is negative
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(Select1 <config.fe.TypeUInt32()> (UDIVrtcall
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(SUB <config.fe.TypeUInt32()> (XOR <config.fe.TypeUInt32()> x (Signmask x)) (Signmask x)) // negate x if negative
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(SUB <config.fe.TypeUInt32()> (XOR <config.fe.TypeUInt32()> y (Signmask y)) (Signmask y)))) // negate y if negative
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(Signmask x)) (Signmask x))
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(Mod32u x y) -> (Select1 <config.fe.TypeUInt32()> (UDIVrtcall x y))
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(Mod16 x y) -> (Mod32 (SignExt16to32 x) (SignExt16to32 y))
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(Mod16u x y) -> (Mod32u (ZeroExt16to32 x) (ZeroExt16to32 y))
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(Mod8 x y) -> (Mod32 (SignExt8to32 x) (SignExt8to32 y))
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(Mod8u x y) -> (Mod32u (ZeroExt8to32 x) (ZeroExt8to32 y))
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(And32 x y) -> (AND x y)
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(And16 x y) -> (AND x y)
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@ -586,8 +596,10 @@
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(MULA (MOVWconst [c]) x a) && c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c) -> (ADD (SLLconst <x.Type> [log2(c/9)] (ADDshiftLL <x.Type> x x [3])) a)
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// div by constant
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(DIVU x (MOVWconst [1])) -> x
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(DIVU x (MOVWconst [c])) && isPowerOfTwo(c) -> (SRLconst [log2(c)] x)
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(Select0 (UDIVrtcall x (MOVWconst [1]))) -> x
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(Select1 (UDIVrtcall _ (MOVWconst [1]))) -> (MOVWconst [0])
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(Select0 (UDIVrtcall x (MOVWconst [c]))) && isPowerOfTwo(c) -> (SRLconst [log2(c)] x)
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(Select1 (UDIVrtcall x (MOVWconst [c]))) && isPowerOfTwo(c) -> (ANDconst [c-1] x)
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// constant comparisons
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(CMPconst (MOVWconst [x]) [y]) && int32(x)==int32(y) -> (FlagEQ)
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@ -805,8 +817,8 @@
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(SRAconst [c] (MOVWconst [d])) -> (MOVWconst [int64(int32(d)>>uint64(c))])
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(MUL (MOVWconst [c]) (MOVWconst [d])) -> (MOVWconst [int64(int32(c*d))])
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(MULA (MOVWconst [c]) (MOVWconst [d]) a) -> (ADDconst [int64(int32(c*d))] a)
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(DIV (MOVWconst [c]) (MOVWconst [d])) -> (MOVWconst [int64(int32(c)/int32(d))])
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(DIVU (MOVWconst [c]) (MOVWconst [d])) -> (MOVWconst [int64(uint32(c)/uint32(d))])
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(Select0 (UDIVrtcall (MOVWconst [c]) (MOVWconst [d]))) -> (MOVWconst [int64(uint32(c)/uint32(d))])
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(Select1 (UDIVrtcall (MOVWconst [c]) (MOVWconst [d]))) -> (MOVWconst [int64(uint32(c)%uint32(d))])
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(ANDconst [c] (MOVWconst [d])) -> (MOVWconst [c&d])
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(ANDconst [c] (ANDconst [d] x)) -> (ANDconst [c&d] x)
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(ORconst [c] (MOVWconst [d])) -> (MOVWconst [c|d])
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@ -138,10 +138,21 @@ func init() {
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{name: "MUL", argLength: 2, reg: gp21, asm: "MUL", commutative: true}, // arg0 * arg1
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{name: "HMUL", argLength: 2, reg: gp21, asm: "MULL", commutative: true}, // (arg0 * arg1) >> 32, signed
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{name: "HMULU", argLength: 2, reg: gp21, asm: "MULLU", commutative: true}, // (arg0 * arg1) >> 32, unsigned
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{name: "DIV", argLength: 2, reg: gp21, asm: "DIV", clobberFlags: true}, // arg0 / arg1, signed, soft div clobbers flags
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{name: "DIVU", argLength: 2, reg: gp21, asm: "DIVU", clobberFlags: true}, // arg0 / arg1, unsighed
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{name: "MOD", argLength: 2, reg: gp21, asm: "MOD", clobberFlags: true}, // arg0 % arg1, signed
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{name: "MODU", argLength: 2, reg: gp21, asm: "MODU", clobberFlags: true}, // arg0 % arg1, unsigned
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// udiv runtime call for soft division
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// output0 = arg0/arg1, output1 = arg0%arg1
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// see ../../../../../runtime/vlop_arm.s
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{
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name: "UDIVrtcall",
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argLength: 2,
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reg: regInfo{
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inputs: []regMask{buildReg("R1"), buildReg("R0")},
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outputs: []regMask{buildReg("R0"), buildReg("R1")},
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clobbers: buildReg("R2 R3"), // also clobbers R12 on NaCl (modified in ../config.go)
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},
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clobberFlags: true,
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typ: "(UInt32,UInt32)",
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},
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{name: "ADDS", argLength: 2, reg: gp21carry, asm: "ADD", commutative: true}, // arg0 + arg1, set carry flag
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{name: "ADDSconst", argLength: 1, reg: gp11carry, asm: "ADD", aux: "Int32"}, // arg0 + auxInt, set carry flag
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@ -623,10 +623,7 @@ const (
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OpARMMUL
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OpARMHMUL
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OpARMHMULU
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OpARMDIV
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OpARMDIVU
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OpARMMOD
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OpARMMODU
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OpARMUDIVrtcall
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OpARMADDS
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OpARMADDSconst
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OpARMADC
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@ -7367,62 +7364,18 @@ var opcodeTable = [...]opInfo{
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},
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},
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{
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name: "DIV",
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name: "UDIVrtcall",
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argLen: 2,
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clobberFlags: true,
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asm: arm.ADIV,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
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{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
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{0, 2}, // R1
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{1, 1}, // R0
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},
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clobbers: 12, // R2 R3
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outputs: []outputInfo{
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{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
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},
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},
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},
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{
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name: "DIVU",
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argLen: 2,
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clobberFlags: true,
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asm: arm.ADIVU,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
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{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
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},
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outputs: []outputInfo{
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{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
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},
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},
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},
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{
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name: "MOD",
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argLen: 2,
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clobberFlags: true,
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asm: arm.AMOD,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
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{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
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},
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outputs: []outputInfo{
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{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
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},
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},
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},
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{
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name: "MODU",
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argLen: 2,
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clobberFlags: true,
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asm: arm.AMODU,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
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{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
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},
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outputs: []outputInfo{
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{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
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{0, 1}, // R0
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{1, 2}, // R1
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},
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},
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},
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@ -110,10 +110,6 @@ func rewriteValueARM(v *Value, config *Config) bool {
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return rewriteValueARM_OpARMCMPshiftRL(v, config)
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case OpARMCMPshiftRLreg:
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return rewriteValueARM_OpARMCMPshiftRLreg(v, config)
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case OpARMDIV:
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return rewriteValueARM_OpARMDIV(v, config)
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case OpARMDIVU:
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return rewriteValueARM_OpARMDIVU(v, config)
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case OpARMEqual:
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return rewriteValueARM_OpARMEqual(v, config)
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case OpARMGreaterEqual:
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@ -676,6 +672,10 @@ func rewriteValueARM(v *Value, config *Config) bool {
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return rewriteValueARM_OpRsh8x64(v, config)
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case OpRsh8x8:
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return rewriteValueARM_OpRsh8x8(v, config)
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case OpSelect0:
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return rewriteValueARM_OpSelect0(v, config)
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case OpSelect1:
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return rewriteValueARM_OpSelect1(v, config)
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case OpSignExt16to32:
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return rewriteValueARM_OpSignExt16to32(v, config)
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case OpSignExt8to16:
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@ -4436,87 +4436,6 @@ func rewriteValueARM_OpARMCMPshiftRLreg(v *Value, config *Config) bool {
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}
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return false
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}
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func rewriteValueARM_OpARMDIV(v *Value, config *Config) bool {
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b := v.Block
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_ = b
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// match: (DIV (MOVWconst [c]) (MOVWconst [d]))
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// cond:
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// result: (MOVWconst [int64(int32(c)/int32(d))])
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for {
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v_0 := v.Args[0]
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if v_0.Op != OpARMMOVWconst {
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break
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}
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c := v_0.AuxInt
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v_1 := v.Args[1]
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if v_1.Op != OpARMMOVWconst {
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break
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}
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d := v_1.AuxInt
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v.reset(OpARMMOVWconst)
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v.AuxInt = int64(int32(c) / int32(d))
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return true
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}
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return false
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}
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func rewriteValueARM_OpARMDIVU(v *Value, config *Config) bool {
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b := v.Block
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_ = b
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// match: (DIVU x (MOVWconst [1]))
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// cond:
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// result: x
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for {
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x := v.Args[0]
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v_1 := v.Args[1]
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if v_1.Op != OpARMMOVWconst {
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break
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}
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if v_1.AuxInt != 1 {
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break
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}
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v.reset(OpCopy)
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v.Type = x.Type
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v.AddArg(x)
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return true
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}
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// match: (DIVU x (MOVWconst [c]))
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// cond: isPowerOfTwo(c)
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// result: (SRLconst [log2(c)] x)
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for {
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x := v.Args[0]
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v_1 := v.Args[1]
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if v_1.Op != OpARMMOVWconst {
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break
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}
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c := v_1.AuxInt
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if !(isPowerOfTwo(c)) {
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break
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}
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v.reset(OpARMSRLconst)
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v.AuxInt = log2(c)
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v.AddArg(x)
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return true
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}
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// match: (DIVU (MOVWconst [c]) (MOVWconst [d]))
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// cond:
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// result: (MOVWconst [int64(uint32(c)/uint32(d))])
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for {
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v_0 := v.Args[0]
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if v_0.Op != OpARMMOVWconst {
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break
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}
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c := v_0.AuxInt
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v_1 := v.Args[1]
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if v_1.Op != OpARMMOVWconst {
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break
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}
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d := v_1.AuxInt
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v.reset(OpARMMOVWconst)
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v.AuxInt = int64(uint32(c) / uint32(d))
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return true
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}
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return false
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}
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func rewriteValueARM_OpARMEqual(v *Value, config *Config) bool {
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b := v.Block
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_ = b
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@ -13347,11 +13266,11 @@ func rewriteValueARM_OpDiv16(v *Value, config *Config) bool {
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_ = b
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// match: (Div16 x y)
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// cond:
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// result: (DIV (SignExt16to32 x) (SignExt16to32 y))
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// result: (Div32 (SignExt16to32 x) (SignExt16to32 y))
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for {
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x := v.Args[0]
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y := v.Args[1]
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v.reset(OpARMDIV)
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v.reset(OpDiv32)
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v0 := b.NewValue0(v.Line, OpSignExt16to32, config.fe.TypeInt32())
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v0.AddArg(x)
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v.AddArg(v0)
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@ -13366,11 +13285,11 @@ func rewriteValueARM_OpDiv16u(v *Value, config *Config) bool {
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_ = b
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// match: (Div16u x y)
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// cond:
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// result: (DIVU (ZeroExt16to32 x) (ZeroExt16to32 y))
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// result: (Div32u (ZeroExt16to32 x) (ZeroExt16to32 y))
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for {
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x := v.Args[0]
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y := v.Args[1]
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v.reset(OpARMDIVU)
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v.reset(OpDiv32u)
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v0 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32())
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v0.AddArg(x)
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v.AddArg(v0)
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@ -13385,13 +13304,51 @@ func rewriteValueARM_OpDiv32(v *Value, config *Config) bool {
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_ = b
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// match: (Div32 x y)
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// cond:
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// result: (DIV x y)
|
||||
// result: (SUB (XOR <config.fe.TypeUInt32()> (Select0 <config.fe.TypeUInt32()> (UDIVrtcall (SUB <config.fe.TypeUInt32()> (XOR x <config.fe.TypeUInt32()> (Signmask x)) (Signmask x)) (SUB <config.fe.TypeUInt32()> (XOR y <config.fe.TypeUInt32()> (Signmask y)) (Signmask y)))) (Signmask (XOR <config.fe.TypeUInt32()> x y))) (Signmask (XOR <config.fe.TypeUInt32()> x y)))
|
||||
for {
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.reset(OpARMDIV)
|
||||
v.AddArg(x)
|
||||
v.AddArg(y)
|
||||
v.reset(OpARMSUB)
|
||||
v0 := b.NewValue0(v.Line, OpARMXOR, config.fe.TypeUInt32())
|
||||
v1 := b.NewValue0(v.Line, OpSelect0, config.fe.TypeUInt32())
|
||||
v2 := b.NewValue0(v.Line, OpARMUDIVrtcall, MakeTuple(config.fe.TypeUInt32(), config.fe.TypeUInt32()))
|
||||
v3 := b.NewValue0(v.Line, OpARMSUB, config.fe.TypeUInt32())
|
||||
v4 := b.NewValue0(v.Line, OpARMXOR, config.fe.TypeUInt32())
|
||||
v4.AddArg(x)
|
||||
v5 := b.NewValue0(v.Line, OpSignmask, config.fe.TypeInt32())
|
||||
v5.AddArg(x)
|
||||
v4.AddArg(v5)
|
||||
v3.AddArg(v4)
|
||||
v6 := b.NewValue0(v.Line, OpSignmask, config.fe.TypeInt32())
|
||||
v6.AddArg(x)
|
||||
v3.AddArg(v6)
|
||||
v2.AddArg(v3)
|
||||
v7 := b.NewValue0(v.Line, OpARMSUB, config.fe.TypeUInt32())
|
||||
v8 := b.NewValue0(v.Line, OpARMXOR, config.fe.TypeUInt32())
|
||||
v8.AddArg(y)
|
||||
v9 := b.NewValue0(v.Line, OpSignmask, config.fe.TypeInt32())
|
||||
v9.AddArg(y)
|
||||
v8.AddArg(v9)
|
||||
v7.AddArg(v8)
|
||||
v10 := b.NewValue0(v.Line, OpSignmask, config.fe.TypeInt32())
|
||||
v10.AddArg(y)
|
||||
v7.AddArg(v10)
|
||||
v2.AddArg(v7)
|
||||
v1.AddArg(v2)
|
||||
v0.AddArg(v1)
|
||||
v11 := b.NewValue0(v.Line, OpSignmask, config.fe.TypeInt32())
|
||||
v12 := b.NewValue0(v.Line, OpARMXOR, config.fe.TypeUInt32())
|
||||
v12.AddArg(x)
|
||||
v12.AddArg(y)
|
||||
v11.AddArg(v12)
|
||||
v0.AddArg(v11)
|
||||
v.AddArg(v0)
|
||||
v13 := b.NewValue0(v.Line, OpSignmask, config.fe.TypeInt32())
|
||||
v14 := b.NewValue0(v.Line, OpARMXOR, config.fe.TypeUInt32())
|
||||
v14.AddArg(x)
|
||||
v14.AddArg(y)
|
||||
v13.AddArg(v14)
|
||||
v.AddArg(v13)
|
||||
return true
|
||||
}
|
||||
}
|
||||
@ -13415,13 +13372,16 @@ func rewriteValueARM_OpDiv32u(v *Value, config *Config) bool {
|
||||
_ = b
|
||||
// match: (Div32u x y)
|
||||
// cond:
|
||||
// result: (DIVU x y)
|
||||
// result: (Select0 <config.fe.TypeUInt32()> (UDIVrtcall x y))
|
||||
for {
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.reset(OpARMDIVU)
|
||||
v.AddArg(x)
|
||||
v.AddArg(y)
|
||||
v.reset(OpSelect0)
|
||||
v.Type = config.fe.TypeUInt32()
|
||||
v0 := b.NewValue0(v.Line, OpARMUDIVrtcall, MakeTuple(config.fe.TypeUInt32(), config.fe.TypeUInt32()))
|
||||
v0.AddArg(x)
|
||||
v0.AddArg(y)
|
||||
v.AddArg(v0)
|
||||
return true
|
||||
}
|
||||
}
|
||||
@ -13445,11 +13405,11 @@ func rewriteValueARM_OpDiv8(v *Value, config *Config) bool {
|
||||
_ = b
|
||||
// match: (Div8 x y)
|
||||
// cond:
|
||||
// result: (DIV (SignExt8to32 x) (SignExt8to32 y))
|
||||
// result: (Div32 (SignExt8to32 x) (SignExt8to32 y))
|
||||
for {
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.reset(OpARMDIV)
|
||||
v.reset(OpDiv32)
|
||||
v0 := b.NewValue0(v.Line, OpSignExt8to32, config.fe.TypeInt32())
|
||||
v0.AddArg(x)
|
||||
v.AddArg(v0)
|
||||
@ -13464,11 +13424,11 @@ func rewriteValueARM_OpDiv8u(v *Value, config *Config) bool {
|
||||
_ = b
|
||||
// match: (Div8u x y)
|
||||
// cond:
|
||||
// result: (DIVU (ZeroExt8to32 x) (ZeroExt8to32 y))
|
||||
// result: (Div32u (ZeroExt8to32 x) (ZeroExt8to32 y))
|
||||
for {
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.reset(OpARMDIVU)
|
||||
v.reset(OpDiv32u)
|
||||
v0 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32())
|
||||
v0.AddArg(x)
|
||||
v.AddArg(v0)
|
||||
@ -14926,11 +14886,11 @@ func rewriteValueARM_OpMod16(v *Value, config *Config) bool {
|
||||
_ = b
|
||||
// match: (Mod16 x y)
|
||||
// cond:
|
||||
// result: (MOD (SignExt16to32 x) (SignExt16to32 y))
|
||||
// result: (Mod32 (SignExt16to32 x) (SignExt16to32 y))
|
||||
for {
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.reset(OpARMMOD)
|
||||
v.reset(OpMod32)
|
||||
v0 := b.NewValue0(v.Line, OpSignExt16to32, config.fe.TypeInt32())
|
||||
v0.AddArg(x)
|
||||
v.AddArg(v0)
|
||||
@ -14945,11 +14905,11 @@ func rewriteValueARM_OpMod16u(v *Value, config *Config) bool {
|
||||
_ = b
|
||||
// match: (Mod16u x y)
|
||||
// cond:
|
||||
// result: (MODU (ZeroExt16to32 x) (ZeroExt16to32 y))
|
||||
// result: (Mod32u (ZeroExt16to32 x) (ZeroExt16to32 y))
|
||||
for {
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.reset(OpARMMODU)
|
||||
v.reset(OpMod32u)
|
||||
v0 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32())
|
||||
v0.AddArg(x)
|
||||
v.AddArg(v0)
|
||||
@ -14964,13 +14924,45 @@ func rewriteValueARM_OpMod32(v *Value, config *Config) bool {
|
||||
_ = b
|
||||
// match: (Mod32 x y)
|
||||
// cond:
|
||||
// result: (MOD x y)
|
||||
// result: (SUB (XOR <config.fe.TypeUInt32()> (Select1 <config.fe.TypeUInt32()> (UDIVrtcall (SUB <config.fe.TypeUInt32()> (XOR <config.fe.TypeUInt32()> x (Signmask x)) (Signmask x)) (SUB <config.fe.TypeUInt32()> (XOR <config.fe.TypeUInt32()> y (Signmask y)) (Signmask y)))) (Signmask x)) (Signmask x))
|
||||
for {
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.reset(OpARMMOD)
|
||||
v.AddArg(x)
|
||||
v.AddArg(y)
|
||||
v.reset(OpARMSUB)
|
||||
v0 := b.NewValue0(v.Line, OpARMXOR, config.fe.TypeUInt32())
|
||||
v1 := b.NewValue0(v.Line, OpSelect1, config.fe.TypeUInt32())
|
||||
v2 := b.NewValue0(v.Line, OpARMUDIVrtcall, MakeTuple(config.fe.TypeUInt32(), config.fe.TypeUInt32()))
|
||||
v3 := b.NewValue0(v.Line, OpARMSUB, config.fe.TypeUInt32())
|
||||
v4 := b.NewValue0(v.Line, OpARMXOR, config.fe.TypeUInt32())
|
||||
v4.AddArg(x)
|
||||
v5 := b.NewValue0(v.Line, OpSignmask, config.fe.TypeInt32())
|
||||
v5.AddArg(x)
|
||||
v4.AddArg(v5)
|
||||
v3.AddArg(v4)
|
||||
v6 := b.NewValue0(v.Line, OpSignmask, config.fe.TypeInt32())
|
||||
v6.AddArg(x)
|
||||
v3.AddArg(v6)
|
||||
v2.AddArg(v3)
|
||||
v7 := b.NewValue0(v.Line, OpARMSUB, config.fe.TypeUInt32())
|
||||
v8 := b.NewValue0(v.Line, OpARMXOR, config.fe.TypeUInt32())
|
||||
v8.AddArg(y)
|
||||
v9 := b.NewValue0(v.Line, OpSignmask, config.fe.TypeInt32())
|
||||
v9.AddArg(y)
|
||||
v8.AddArg(v9)
|
||||
v7.AddArg(v8)
|
||||
v10 := b.NewValue0(v.Line, OpSignmask, config.fe.TypeInt32())
|
||||
v10.AddArg(y)
|
||||
v7.AddArg(v10)
|
||||
v2.AddArg(v7)
|
||||
v1.AddArg(v2)
|
||||
v0.AddArg(v1)
|
||||
v11 := b.NewValue0(v.Line, OpSignmask, config.fe.TypeInt32())
|
||||
v11.AddArg(x)
|
||||
v0.AddArg(v11)
|
||||
v.AddArg(v0)
|
||||
v12 := b.NewValue0(v.Line, OpSignmask, config.fe.TypeInt32())
|
||||
v12.AddArg(x)
|
||||
v.AddArg(v12)
|
||||
return true
|
||||
}
|
||||
}
|
||||
@ -14979,13 +14971,16 @@ func rewriteValueARM_OpMod32u(v *Value, config *Config) bool {
|
||||
_ = b
|
||||
// match: (Mod32u x y)
|
||||
// cond:
|
||||
// result: (MODU x y)
|
||||
// result: (Select1 <config.fe.TypeUInt32()> (UDIVrtcall x y))
|
||||
for {
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.reset(OpARMMODU)
|
||||
v.AddArg(x)
|
||||
v.AddArg(y)
|
||||
v.reset(OpSelect1)
|
||||
v.Type = config.fe.TypeUInt32()
|
||||
v0 := b.NewValue0(v.Line, OpARMUDIVrtcall, MakeTuple(config.fe.TypeUInt32(), config.fe.TypeUInt32()))
|
||||
v0.AddArg(x)
|
||||
v0.AddArg(y)
|
||||
v.AddArg(v0)
|
||||
return true
|
||||
}
|
||||
}
|
||||
@ -14994,11 +14989,11 @@ func rewriteValueARM_OpMod8(v *Value, config *Config) bool {
|
||||
_ = b
|
||||
// match: (Mod8 x y)
|
||||
// cond:
|
||||
// result: (MOD (SignExt8to32 x) (SignExt8to32 y))
|
||||
// result: (Mod32 (SignExt8to32 x) (SignExt8to32 y))
|
||||
for {
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.reset(OpARMMOD)
|
||||
v.reset(OpMod32)
|
||||
v0 := b.NewValue0(v.Line, OpSignExt8to32, config.fe.TypeInt32())
|
||||
v0.AddArg(x)
|
||||
v.AddArg(v0)
|
||||
@ -15013,11 +15008,11 @@ func rewriteValueARM_OpMod8u(v *Value, config *Config) bool {
|
||||
_ = b
|
||||
// match: (Mod8u x y)
|
||||
// cond:
|
||||
// result: (MODU (ZeroExt8to32 x) (ZeroExt8to32 y))
|
||||
// result: (Mod32u (ZeroExt8to32 x) (ZeroExt8to32 y))
|
||||
for {
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.reset(OpARMMODU)
|
||||
v.reset(OpMod32u)
|
||||
v0 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32())
|
||||
v0.AddArg(x)
|
||||
v.AddArg(v0)
|
||||
@ -16344,6 +16339,144 @@ func rewriteValueARM_OpRsh8x8(v *Value, config *Config) bool {
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValueARM_OpSelect0(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (Select0 (UDIVrtcall x (MOVWconst [1])))
|
||||
// cond:
|
||||
// result: x
|
||||
for {
|
||||
v_0 := v.Args[0]
|
||||
if v_0.Op != OpARMUDIVrtcall {
|
||||
break
|
||||
}
|
||||
x := v_0.Args[0]
|
||||
v_0_1 := v_0.Args[1]
|
||||
if v_0_1.Op != OpARMMOVWconst {
|
||||
break
|
||||
}
|
||||
if v_0_1.AuxInt != 1 {
|
||||
break
|
||||
}
|
||||
v.reset(OpCopy)
|
||||
v.Type = x.Type
|
||||
v.AddArg(x)
|
||||
return true
|
||||
}
|
||||
// match: (Select0 (UDIVrtcall x (MOVWconst [c])))
|
||||
// cond: isPowerOfTwo(c)
|
||||
// result: (SRLconst [log2(c)] x)
|
||||
for {
|
||||
v_0 := v.Args[0]
|
||||
if v_0.Op != OpARMUDIVrtcall {
|
||||
break
|
||||
}
|
||||
x := v_0.Args[0]
|
||||
v_0_1 := v_0.Args[1]
|
||||
if v_0_1.Op != OpARMMOVWconst {
|
||||
break
|
||||
}
|
||||
c := v_0_1.AuxInt
|
||||
if !(isPowerOfTwo(c)) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMSRLconst)
|
||||
v.AuxInt = log2(c)
|
||||
v.AddArg(x)
|
||||
return true
|
||||
}
|
||||
// match: (Select0 (UDIVrtcall (MOVWconst [c]) (MOVWconst [d])))
|
||||
// cond:
|
||||
// result: (MOVWconst [int64(uint32(c)/uint32(d))])
|
||||
for {
|
||||
v_0 := v.Args[0]
|
||||
if v_0.Op != OpARMUDIVrtcall {
|
||||
break
|
||||
}
|
||||
v_0_0 := v_0.Args[0]
|
||||
if v_0_0.Op != OpARMMOVWconst {
|
||||
break
|
||||
}
|
||||
c := v_0_0.AuxInt
|
||||
v_0_1 := v_0.Args[1]
|
||||
if v_0_1.Op != OpARMMOVWconst {
|
||||
break
|
||||
}
|
||||
d := v_0_1.AuxInt
|
||||
v.reset(OpARMMOVWconst)
|
||||
v.AuxInt = int64(uint32(c) / uint32(d))
|
||||
return true
|
||||
}
|
||||
return false
|
||||
}
|
||||
func rewriteValueARM_OpSelect1(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (Select1 (UDIVrtcall _ (MOVWconst [1])))
|
||||
// cond:
|
||||
// result: (MOVWconst [0])
|
||||
for {
|
||||
v_0 := v.Args[0]
|
||||
if v_0.Op != OpARMUDIVrtcall {
|
||||
break
|
||||
}
|
||||
v_0_1 := v_0.Args[1]
|
||||
if v_0_1.Op != OpARMMOVWconst {
|
||||
break
|
||||
}
|
||||
if v_0_1.AuxInt != 1 {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMMOVWconst)
|
||||
v.AuxInt = 0
|
||||
return true
|
||||
}
|
||||
// match: (Select1 (UDIVrtcall x (MOVWconst [c])))
|
||||
// cond: isPowerOfTwo(c)
|
||||
// result: (ANDconst [c-1] x)
|
||||
for {
|
||||
v_0 := v.Args[0]
|
||||
if v_0.Op != OpARMUDIVrtcall {
|
||||
break
|
||||
}
|
||||
x := v_0.Args[0]
|
||||
v_0_1 := v_0.Args[1]
|
||||
if v_0_1.Op != OpARMMOVWconst {
|
||||
break
|
||||
}
|
||||
c := v_0_1.AuxInt
|
||||
if !(isPowerOfTwo(c)) {
|
||||
break
|
||||
}
|
||||
v.reset(OpARMANDconst)
|
||||
v.AuxInt = c - 1
|
||||
v.AddArg(x)
|
||||
return true
|
||||
}
|
||||
// match: (Select1 (UDIVrtcall (MOVWconst [c]) (MOVWconst [d])))
|
||||
// cond:
|
||||
// result: (MOVWconst [int64(uint32(c)%uint32(d))])
|
||||
for {
|
||||
v_0 := v.Args[0]
|
||||
if v_0.Op != OpARMUDIVrtcall {
|
||||
break
|
||||
}
|
||||
v_0_0 := v_0.Args[0]
|
||||
if v_0_0.Op != OpARMMOVWconst {
|
||||
break
|
||||
}
|
||||
c := v_0_0.AuxInt
|
||||
v_0_1 := v_0.Args[1]
|
||||
if v_0_1.Op != OpARMMOVWconst {
|
||||
break
|
||||
}
|
||||
d := v_0_1.AuxInt
|
||||
v.reset(OpARMMOVWconst)
|
||||
v.AuxInt = int64(uint32(c) % uint32(d))
|
||||
return true
|
||||
}
|
||||
return false
|
||||
}
|
||||
func rewriteValueARM_OpSignExt16to32(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
|
||||
@ -107,6 +107,7 @@ TEXT runtime·_sfloatpanic(SB),NOSPLIT,$-4
|
||||
B runtime·sigpanic(SB)
|
||||
|
||||
// func udiv(n, d uint32) (q, r uint32)
|
||||
// compiler knowns the register usage of this function
|
||||
// Reference:
|
||||
// Sloss, Andrew et. al; ARM System Developer's Guide: Designing and Optimizing System Software
|
||||
// Morgan Kaufmann; 1 edition (April 8, 2004), ISBN 978-1558608740
|
||||
@ -117,7 +118,7 @@ TEXT runtime·_sfloatpanic(SB),NOSPLIT,$-4
|
||||
#define Ra R11
|
||||
|
||||
// Be careful: Ra == R11 will be used by the linker for synthesized instructions.
|
||||
TEXT udiv<>(SB),NOSPLIT,$-4
|
||||
TEXT udiv(SB),NOSPLIT,$-4
|
||||
CLZ Rq, Rs // find normalizing shift
|
||||
MOVW.S Rq<<Rs, Ra
|
||||
MOVW $fast_udiv_tab<>-64(SB), RM
|
||||
@ -227,7 +228,7 @@ TEXT _divu(SB), NOSPLIT, $16-0
|
||||
MOVW RTMP, Rr /* numerator */
|
||||
MOVW g_m(g), Rq
|
||||
MOVW m_divmod(Rq), Rq /* denominator */
|
||||
BL udiv<>(SB)
|
||||
BL udiv(SB)
|
||||
MOVW Rq, RTMP
|
||||
MOVW 4(R13), Rq
|
||||
MOVW 8(R13), Rr
|
||||
@ -245,7 +246,7 @@ TEXT _modu(SB), NOSPLIT, $16-0
|
||||
MOVW RTMP, Rr /* numerator */
|
||||
MOVW g_m(g), Rq
|
||||
MOVW m_divmod(Rq), Rq /* denominator */
|
||||
BL udiv<>(SB)
|
||||
BL udiv(SB)
|
||||
MOVW Rr, RTMP
|
||||
MOVW 4(R13), Rq
|
||||
MOVW 8(R13), Rr
|
||||
@ -269,7 +270,7 @@ TEXT _div(SB),NOSPLIT,$16-0
|
||||
BGE d2
|
||||
RSB $0, Rq, Rq
|
||||
d0:
|
||||
BL udiv<>(SB) /* none/both neg */
|
||||
BL udiv(SB) /* none/both neg */
|
||||
MOVW Rq, RTMP
|
||||
B out1
|
||||
d1:
|
||||
@ -277,8 +278,8 @@ d1:
|
||||
BGE d0
|
||||
RSB $0, Rq, Rq
|
||||
d2:
|
||||
BL udiv<>(SB) /* one neg */
|
||||
RSB $0, Rq, RTMP
|
||||
BL udiv(SB) /* one neg */
|
||||
RSB $0, Rq, RTMP
|
||||
out1:
|
||||
MOVW 4(R13), Rq
|
||||
MOVW 8(R13), Rr
|
||||
@ -300,11 +301,11 @@ TEXT _mod(SB),NOSPLIT,$16-0
|
||||
CMP $0, Rr
|
||||
BGE m1
|
||||
RSB $0, Rr, Rr
|
||||
BL udiv<>(SB) /* neg numerator */
|
||||
BL udiv(SB) /* neg numerator */
|
||||
RSB $0, Rr, RTMP
|
||||
B out
|
||||
m1:
|
||||
BL udiv<>(SB) /* pos numerator */
|
||||
BL udiv(SB) /* pos numerator */
|
||||
MOVW Rr, RTMP
|
||||
out:
|
||||
MOVW 4(R13), Rq
|
||||
|
||||
Loading…
Reference in New Issue
Block a user