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cmd/internal/obj/riscv: avoid obj.Prog rewriting for address to register loads
Rather than rewriting the obj.Prog for a MOV pseudo-instruction targeting an address to register load, generate the appropriate machine instruction sequence directly. Change-Id: I507195b6d24ff3253eadcc807ddbe27dca97d220 Reviewed-on: https://go-review.googlesource.com/c/go/+/344456 Trust: Joel Sing <joel@sing.id.au> Reviewed-by: Cherry Mui <cherryyz@google.com>
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@ -278,39 +278,15 @@ func rewriteMOV(ctxt *obj.Link, newprog obj.ProgAlloc, p *obj.Prog) {
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ctxt.Diag("%v: constant load must target register", p)
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}
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case obj.TYPE_ADDR: // MOV $sym+off(SP/SB), R
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case obj.TYPE_ADDR:
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if p.To.Type != obj.TYPE_REG || p.As != AMOV {
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ctxt.Diag("unsupported addr MOV at %v", p)
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}
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switch p.From.Name {
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case obj.NAME_AUTO, obj.NAME_PARAM, obj.NAME_NONE:
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case obj.NAME_EXTERN, obj.NAME_STATIC:
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// AUIPC $off_hi, R
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// ADDI $off_lo, R
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to := p.To
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p.As = AAUIPC
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p.Mark |= NEED_PCREL_ITYPE_RELOC
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p.SetFrom3(obj.Addr{Type: obj.TYPE_CONST, Offset: p.From.Offset, Sym: p.From.Sym})
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p.From = obj.Addr{Type: obj.TYPE_CONST, Offset: 0}
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p.Reg = 0
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p.To = to
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p = obj.Appendp(p, newprog)
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p.As = AADDI
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p.From = obj.Addr{Type: obj.TYPE_CONST}
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p.Reg = to.Reg
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p.To = to
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case obj.NAME_PARAM, obj.NAME_AUTO:
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p.As = AADDI
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p.Reg = REG_SP
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p.From.Type = obj.TYPE_CONST
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case obj.NAME_NONE:
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p.As = AADDI
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p.Reg = p.From.Reg
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p.From.Type = obj.TYPE_CONST
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p.From.Reg = 0
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default:
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ctxt.Diag("bad addr MOV from name %v at %v", p.From.Name, p)
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@ -1645,6 +1621,57 @@ func instructionForProg(p *obj.Prog) *instruction {
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return ins
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}
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// instructionsForOpImmediate returns the machine instructions for a immedate
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// operand. The instruction is specified by as and the source register is
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// specified by rs, instead of the obj.Prog.
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func instructionsForOpImmediate(p *obj.Prog, as obj.As, rs int16) []*instruction {
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// <opi> $imm, REG, TO
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ins := instructionForProg(p)
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ins.as, ins.rs1 = as, uint32(rs)
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low, high, err := Split32BitImmediate(ins.imm)
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if err != nil {
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p.Ctxt.Diag("%v: constant %d too large", p, ins.imm, err)
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return nil
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}
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if high == 0 {
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return []*instruction{ins}
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}
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// Split into two additions, if possible.
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if ins.as == AADDI && ins.imm >= -(1<<12) && ins.imm < 1<<12-1 {
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imm0 := ins.imm / 2
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imm1 := ins.imm - imm0
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// ADDI $(imm/2), REG, TO
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// ADDI $(imm-imm/2), TO, TO
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ins.imm = imm0
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insADDI := &instruction{as: AADDI, rd: ins.rd, rs1: ins.rd, imm: imm1}
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return []*instruction{ins, insADDI}
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}
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// LUI $high, TMP
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// ADDI $low, TMP, TMP
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// <op> TMP, REG, TO
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insLUI := &instruction{as: ALUI, rd: REG_TMP, imm: high}
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insADDIW := &instruction{as: AADDIW, rd: REG_TMP, rs1: REG_TMP, imm: low}
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switch ins.as {
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case AADDI:
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ins.as = AADD
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case AANDI:
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ins.as = AAND
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case AORI:
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ins.as = AOR
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case AXORI:
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ins.as = AXOR
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default:
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p.Ctxt.Diag("unsupported immediate instruction %v for splitting", p)
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return nil
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}
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ins.rs2 = REG_TMP
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return []*instruction{insLUI, insADDIW, ins}
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}
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// instructionsForLoad returns the machine instructions for a load. The load
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// instruction is specified by as and the base/source register is specified
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// by rs, instead of the obj.Prog.
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@ -1797,6 +1824,9 @@ func instructionsForMOV(p *obj.Prog) []*instruction {
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inss = instructionsForLoad(p, movToLoad(p.As), addrToReg(p.From))
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case obj.NAME_EXTERN, obj.NAME_STATIC:
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// Note that the values for $off_hi and $off_lo are currently
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// zero and will be assigned during relocation.
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//
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// AUIPC $off_hi, Rd
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// L $off_lo, Rd, Rd
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insAUIPC := &instruction{as: AAUIPC, rd: ins.rd}
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@ -1817,6 +1847,9 @@ func instructionsForMOV(p *obj.Prog) []*instruction {
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inss = instructionsForStore(p, movToStore(p.As), addrToReg(p.To))
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case obj.NAME_EXTERN, obj.NAME_STATIC:
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// Note that the values for $off_hi and $off_lo are currently
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// zero and will be assigned during relocation.
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//
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// AUIPC $off_hi, Rtmp
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// S $off_lo, Rtmp, Rd
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insAUIPC := &instruction{as: AAUIPC, rd: REG_TMP}
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@ -1824,6 +1857,24 @@ func instructionsForMOV(p *obj.Prog) []*instruction {
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inss = []*instruction{insAUIPC, ins}
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}
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case p.From.Type == obj.TYPE_ADDR && p.To.Type == obj.TYPE_REG:
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// MOV $sym+off(SP/SB), R
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switch p.From.Name {
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case obj.NAME_AUTO, obj.NAME_PARAM, obj.NAME_NONE:
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inss = instructionsForOpImmediate(p, AADDI, addrToReg(p.From))
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case obj.NAME_EXTERN, obj.NAME_STATIC:
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// Note that the values for $off_hi and $off_lo are currently
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// zero and will be assigned during relocation.
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//
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// AUIPC $off_hi, R
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// ADDI $off_lo, R
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insAUIPC := &instruction{as: AAUIPC, rd: ins.rd}
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ins.as, ins.rs1, ins.rs2, ins.imm = AADDI, ins.rd, obj.REG_NONE, 0
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inss = []*instruction{insAUIPC, ins}
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}
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default:
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// If we get here with a MOV pseudo-instruction it is going to
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// remain unhandled. For now we trust rewriteMOV to catch these.
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@ -1891,49 +1942,7 @@ func instructionsForProg(p *obj.Prog) []*instruction {
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ins.rs1, ins.rs2 = uint32(p.From.Reg), REG_ZERO
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case AADDI, AANDI, AORI, AXORI:
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// <opi> $imm, REG, TO
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low, high, err := Split32BitImmediate(ins.imm)
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if err != nil {
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p.Ctxt.Diag("%v: constant %d too large", p, ins.imm, err)
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return nil
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}
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if high == 0 {
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break
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}
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// Split into two additions if possible.
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if ins.as == AADDI && ins.imm >= -(1<<12) && ins.imm < 1<<12-1 {
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imm0 := ins.imm / 2
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imm1 := ins.imm - imm0
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// ADDI $(imm/2), REG, TO
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// ADDI $(imm-imm/2), TO, TO
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ins.imm = imm0
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insADDI := &instruction{as: AADDI, rd: ins.rd, rs1: ins.rd, imm: imm1}
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inss = append(inss, insADDI)
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break
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}
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// LUI $high, TMP
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// ADDI $low, TMP, TMP
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// <op> TMP, REG, TO
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insLUI := &instruction{as: ALUI, rd: REG_TMP, imm: high}
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insADDIW := &instruction{as: AADDIW, rd: REG_TMP, rs1: REG_TMP, imm: low}
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switch ins.as {
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case AADDI:
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ins.as = AADD
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case AANDI:
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ins.as = AAND
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case AORI:
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ins.as = AOR
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case AXORI:
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ins.as = AXOR
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default:
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p.Ctxt.Diag("unsupported instruction %v for splitting", p)
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return nil
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}
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ins.rs2 = REG_TMP
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inss = []*instruction{insLUI, insADDIW, ins}
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inss = instructionsForOpImmediate(p, ins.as, p.Reg)
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case ASCW, ASCD, AAMOSWAPW, AAMOSWAPD, AAMOADDW, AAMOADDD, AAMOANDW, AAMOANDD, AAMOORW, AAMOORD,
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AAMOXORW, AAMOXORD, AAMOMINW, AAMOMIND, AAMOMINUW, AAMOMINUD, AAMOMAXW, AAMOMAXD, AAMOMAXUW, AAMOMAXUD:
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