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cmd/compile: improve the implementation of Lowered{Move,Zero} on linux/loong64
Like the CL 487295, when implementing Lowered{Move,Zero}, 8 is first subtracted
from Rarg0 (parameter Ptr), and then the offset of 8 is added during subsequent
operations on Rarg0. This operation is meaningless, so delete it.
Change LoweredMove's Rarg0 register to R20, consistent with duffcopy.
goos: linux
goarch: loong64
pkg: runtime
cpu: Loongson-3C5000 @ 2200.00MHz
│ old.bench │ new.bench │
│ sec/op │ sec/op vs base │
Memmove/15 19.10n ± 0% 19.10n ± 0% ~ (p=0.483 n=15)
MemmoveUnalignedDst/15 25.02n ± 0% 25.02n ± 0% ~ (p=0.741 n=15)
MemmoveUnalignedDst/32 48.22n ± 0% 48.22n ± 0% ~ (p=1.000 n=15) ¹
MemmoveUnalignedDst/64 90.57n ± 0% 90.52n ± 0% ~ (p=0.212 n=15)
MemmoveUnalignedDstOverlap/32 44.12n ± 0% 44.13n ± 0% +0.02% (p=0.000 n=15)
MemmoveUnalignedDstOverlap/64 87.79n ± 0% 87.80n ± 0% +0.01% (p=0.002 n=15)
MemmoveUnalignedSrc/0 3.639n ± 0% 3.639n ± 0% ~ (p=1.000 n=15) ¹
MemmoveUnalignedSrc/1 7.733n ± 0% 7.733n ± 0% ~ (p=1.000 n=15)
MemmoveUnalignedSrc/2 9.097n ± 0% 9.097n ± 0% ~ (p=1.000 n=15)
MemmoveUnalignedSrc/3 10.46n ± 0% 10.46n ± 0% ~ (p=1.000 n=15) ¹
MemmoveUnalignedSrc/4 11.83n ± 0% 11.83n ± 0% ~ (p=1.000 n=15) ¹
MemmoveUnalignedSrc/64 93.71n ± 0% 93.70n ± 0% ~ (p=0.128 n=15)
Memclr/4096 699.1n ± 0% 699.1n ± 0% ~ (p=0.682 n=15)
Memclr/65536 11.18µ ± 0% 11.18µ ± 0% -0.01% (p=0.000 n=15)
Memclr/1M 175.2µ ± 0% 175.2µ ± 0% ~ (p=0.191 n=15)
Memclr/4M 661.8µ ± 0% 662.0µ ± 0% ~ (p=0.486 n=15)
MemclrUnaligned/4_5 19.39n ± 0% 20.47n ± 0% +5.57% (p=0.000 n=15)
MemclrUnaligned/4_16 22.29n ± 0% 21.38n ± 0% -4.08% (p=0.000 n=15)
MemclrUnaligned/4_64 30.58n ± 0% 29.81n ± 0% -2.52% (p=0.000 n=15)
MemclrUnaligned/4_65536 11.19µ ± 0% 11.20µ ± 0% +0.02% (p=0.000 n=15)
GoMemclr/5 12.73n ± 0% 12.73n ± 0% ~ (p=0.261 n=15)
GoMemclr/16 10.01n ± 0% 10.00n ± 0% ~ (p=0.264 n=15)
GoMemclr/256 50.94n ± 0% 50.94n ± 0% ~ (p=0.372 n=15)
ClearFat15 14.95n ± 0% 15.01n ± 4% ~ (p=0.925 n=15)
ClearFat1032 125.5n ± 0% 125.6n ± 0% +0.08% (p=0.000 n=15)
CopyFat64 10.58n ± 0% 10.01n ± 0% -5.39% (p=0.000 n=15)
CopyFat1040 244.3n ± 0% 155.6n ± 0% -36.31% (p=0.000 n=15)
Issue18740/2byte 29.82µ ± 0% 29.82µ ± 0% ~ (p=0.648 n=30)
Issue18740/4byte 18.18µ ± 0% 18.18µ ± 0% -0.02% (p=0.001 n=30)
Issue18740/8byte 8.395µ ± 0% 8.395µ ± 0% ~ (p=0.401 n=30)
geomean 154.5n 151.8n -1.70%
¹ all samples are equal
Change-Id: Ia3f3c8b25e1e93c97ab72328651de78ca9dec016
Reviewed-on: https://go-review.googlesource.com/c/go/+/488515
Reviewed-by: Keith Randall <khr@golang.org>
Reviewed-by: Bryan Mills <bcmills@google.com>
Auto-Submit: Ian Lance Taylor <iant@golang.org>
Reviewed-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: xiaodong liu <teaofmoli@gmail.com>
Reviewed-by: Keith Randall <khr@google.com>
Reviewed-by: Meidan Li <limeidan@loongson.cn>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
This commit is contained in:
Guoqi Chen
Gopher Robot
parent
c729dc187a
commit
3754ca0af2
@ -80,6 +80,28 @@ func storeByType(t *types.Type, r int16) obj.As {
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panic("bad store type")
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}
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// largestMove returns the largest move instruction possible and its size,
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// given the alignment of the total size of the move.
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//
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// e.g., a 16-byte move may use MOVV, but an 11-byte move must use MOVB.
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//
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// Note that the moves may not be on naturally aligned addresses depending on
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// the source and destination.
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//
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// This matches the calculation in ssa.moveSize.
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func largestMove(alignment int64) (obj.As, int64) {
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switch {
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case alignment%8 == 0:
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return loong64.AMOVV, 8
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case alignment%4 == 0:
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return loong64.AMOVW, 4
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case alignment%2 == 0:
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return loong64.AMOVH, 2
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default:
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return loong64.AMOVB, 1
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}
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}
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func ssaGenValue(s *ssagen.State, v *ssa.Value) {
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switch v.Op {
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case ssa.OpCopy, ssa.OpLOONG64MOVVreg:
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@ -348,49 +370,29 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
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p.To.Offset = v.AuxInt
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case ssa.OpLOONG64LoweredZero:
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// SUBV $8, R19
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// MOVV R0, 8(R19)
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// ADDV $8, R19
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// BNE Rarg1, R19, -2(PC)
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// arg1 is the address of the last element to zero
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var sz int64
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var mov obj.As
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switch {
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case v.AuxInt%8 == 0:
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sz = 8
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mov = loong64.AMOVV
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case v.AuxInt%4 == 0:
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sz = 4
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mov = loong64.AMOVW
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case v.AuxInt%2 == 0:
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sz = 2
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mov = loong64.AMOVH
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default:
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sz = 1
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mov = loong64.AMOVB
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}
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p := s.Prog(loong64.ASUBVU)
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p.From.Type = obj.TYPE_CONST
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p.From.Offset = sz
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p.To.Type = obj.TYPE_REG
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p.To.Reg = loong64.REG_R19
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p2 := s.Prog(mov)
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p2.From.Type = obj.TYPE_REG
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p2.From.Reg = loong64.REGZERO
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p2.To.Type = obj.TYPE_MEM
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p2.To.Reg = loong64.REG_R19
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p2.To.Offset = sz
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p3 := s.Prog(loong64.AADDVU)
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p3.From.Type = obj.TYPE_CONST
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p3.From.Offset = sz
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p3.To.Type = obj.TYPE_REG
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p3.To.Reg = loong64.REG_R19
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p4 := s.Prog(loong64.ABNE)
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p4.From.Type = obj.TYPE_REG
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p4.From.Reg = v.Args[1].Reg()
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p4.Reg = loong64.REG_R19
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p4.To.Type = obj.TYPE_BRANCH
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p4.To.SetTarget(p2)
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// MOVx R0, (Rarg0)
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// ADDV $sz, Rarg0
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// BGEU Rarg1, Rarg0, -2(PC)
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mov, sz := largestMove(v.AuxInt)
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p := s.Prog(mov)
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p.From.Type = obj.TYPE_REG
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p.From.Reg = loong64.REGZERO
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p.To.Type = obj.TYPE_MEM
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p.To.Reg = v.Args[0].Reg()
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p2 := s.Prog(loong64.AADDVU)
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p2.From.Type = obj.TYPE_CONST
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p2.From.Offset = sz
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p2.To.Type = obj.TYPE_REG
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p2.To.Reg = v.Args[0].Reg()
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p3 := s.Prog(loong64.ABGEU)
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p3.From.Type = obj.TYPE_REG
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p3.From.Reg = v.Args[1].Reg()
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p3.Reg = v.Args[0].Reg()
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p3.To.Type = obj.TYPE_BRANCH
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p3.To.SetTarget(p)
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case ssa.OpLOONG64DUFFCOPY:
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p := s.Prog(obj.ADUFFCOPY)
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p.To.Type = obj.TYPE_MEM
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@ -398,61 +400,43 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
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p.To.Sym = ir.Syms.Duffcopy
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p.To.Offset = v.AuxInt
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case ssa.OpLOONG64LoweredMove:
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// SUBV $8, R19
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// MOVV 8(R19), Rtmp
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// MOVV Rtmp, (R4)
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// ADDV $8, R19
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// ADDV $8, R4
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// BNE Rarg2, R19, -4(PC)
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// arg2 is the address of the last element of src
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var sz int64
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var mov obj.As
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switch {
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case v.AuxInt%8 == 0:
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sz = 8
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mov = loong64.AMOVV
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case v.AuxInt%4 == 0:
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sz = 4
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mov = loong64.AMOVW
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case v.AuxInt%2 == 0:
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sz = 2
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mov = loong64.AMOVH
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default:
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sz = 1
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mov = loong64.AMOVB
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}
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p := s.Prog(loong64.ASUBVU)
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p.From.Type = obj.TYPE_CONST
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p.From.Offset = sz
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// MOVx (Rarg1), Rtmp
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// MOVx Rtmp, (Rarg0)
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// ADDV $sz, Rarg1
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// ADDV $sz, Rarg0
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// BGEU Rarg2, Rarg0, -4(PC)
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mov, sz := largestMove(v.AuxInt)
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p := s.Prog(mov)
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p.From.Type = obj.TYPE_MEM
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p.From.Reg = v.Args[1].Reg()
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p.To.Type = obj.TYPE_REG
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p.To.Reg = loong64.REG_R19
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p.To.Reg = loong64.REGTMP
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p2 := s.Prog(mov)
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p2.From.Type = obj.TYPE_MEM
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p2.From.Reg = loong64.REG_R19
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p2.From.Offset = sz
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p2.To.Type = obj.TYPE_REG
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p2.To.Reg = loong64.REGTMP
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p3 := s.Prog(mov)
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p3.From.Type = obj.TYPE_REG
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p3.From.Reg = loong64.REGTMP
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p3.To.Type = obj.TYPE_MEM
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p3.To.Reg = loong64.REG_R4
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p2.From.Type = obj.TYPE_REG
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p2.From.Reg = loong64.REGTMP
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p2.To.Type = obj.TYPE_MEM
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p2.To.Reg = v.Args[0].Reg()
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p3 := s.Prog(loong64.AADDVU)
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p3.From.Type = obj.TYPE_CONST
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p3.From.Offset = sz
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p3.To.Type = obj.TYPE_REG
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p3.To.Reg = v.Args[1].Reg()
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p4 := s.Prog(loong64.AADDVU)
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p4.From.Type = obj.TYPE_CONST
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p4.From.Offset = sz
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p4.To.Type = obj.TYPE_REG
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p4.To.Reg = loong64.REG_R19
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p5 := s.Prog(loong64.AADDVU)
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p5.From.Type = obj.TYPE_CONST
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p5.From.Offset = sz
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p5.To.Type = obj.TYPE_REG
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p5.To.Reg = loong64.REG_R4
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p6 := s.Prog(loong64.ABNE)
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p6.From.Type = obj.TYPE_REG
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p6.From.Reg = v.Args[2].Reg()
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p6.Reg = loong64.REG_R19
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p6.To.Type = obj.TYPE_BRANCH
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p6.To.SetTarget(p2)
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p4.To.Reg = v.Args[0].Reg()
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p5 := s.Prog(loong64.ABGEU)
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p5.From.Type = obj.TYPE_REG
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p5.From.Reg = v.Args[2].Reg()
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p5.Reg = v.Args[1].Reg()
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p5.To.Type = obj.TYPE_BRANCH
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p5.To.SetTarget(p)
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case ssa.OpLOONG64CALLstatic, ssa.OpLOONG64CALLclosure, ssa.OpLOONG64CALLinter:
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s.Call(v)
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case ssa.OpLOONG64CALLtail:
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@ -321,10 +321,9 @@ func init() {
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// arg2 = mem
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// auxint = alignment
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// returns mem
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// SUBV $8, R19
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// MOVV R0, 8(R19)
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// ADDV $8, R19
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// BNE Rarg1, R19, -2(PC)
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// MOVx R0, (R19)
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// ADDV $sz, R19
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// BGEU Rarg1, R19, -2(PC)
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{
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name: "LoweredZero",
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aux: "Int64",
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@ -333,32 +332,31 @@ func init() {
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inputs: []regMask{buildReg("R19"), gp},
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clobbers: buildReg("R19"),
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},
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clobberFlags: true,
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typ: "Mem",
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faultOnNilArg0: true,
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},
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// large or unaligned move
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// arg0 = address of dst memory (in R4, changed as side effect)
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// arg0 = address of dst memory (in R20, changed as side effect)
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// arg1 = address of src memory (in R19, changed as side effect)
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// arg2 = address of the last element of src
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// arg3 = mem
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// auxint = alignment
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// returns mem
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// SUBV $8, R19
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// MOVV 8(R19), Rtmp
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// MOVV Rtmp, (R4)
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// ADDV $8, R19
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// ADDV $8, R4
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// BNE Rarg2, R19, -4(PC)
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// MOVx (R19), Rtmp
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// MOVx Rtmp, (R20)
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// ADDV $sz, R19
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// ADDV $sz, R20
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// BGEU Rarg2, R19, -4(PC)
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{
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name: "LoweredMove",
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aux: "Int64",
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argLength: 4,
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reg: regInfo{
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inputs: []regMask{buildReg("R4"), buildReg("R19"), gp},
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clobbers: buildReg("R19 R4"),
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inputs: []regMask{buildReg("R20"), buildReg("R19"), gp},
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clobbers: buildReg("R19 R20"),
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},
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clobberFlags: true,
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typ: "Mem",
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faultOnNilArg0: true,
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faultOnNilArg1: true,
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},
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@ -24565,7 +24565,6 @@ var opcodeTable = [...]opInfo{
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name: "LoweredZero",
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auxType: auxInt64,
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argLen: 3,
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clobberFlags: true,
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faultOnNilArg0: true,
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reg: regInfo{
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inputs: []inputInfo{
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@ -24579,16 +24578,15 @@ var opcodeTable = [...]opInfo{
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name: "LoweredMove",
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auxType: auxInt64,
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argLen: 4,
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clobberFlags: true,
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faultOnNilArg0: true,
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faultOnNilArg1: true,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 8}, // R4
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{0, 524288}, // R20
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{1, 262144}, // R19
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{2, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
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},
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clobbers: 262152, // R4 R19
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clobbers: 786432, // R19 R20
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},
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},
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{
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