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cmd/compile: add amd64 LEAL{1,2,4,8} ops
For future use in rewrite rules. Change-Id: Ic9875beb0dea6e0bbcbd4b75d99a53f4a9a7c3fd Reviewed-on: https://go-review.googlesource.com/101275 Run-TryBot: Josh Bleecher Snyder <josharian@gmail.com> TryBot-Result: Gobot Gobot <gobot@golang.org> Reviewed-by: Brad Fitzpatrick <bradfitz@golang.org>
This commit is contained in:
Josh Bleecher Snyder
parent
8e3dd8ab88
commit
22115859a5
@ -521,21 +521,23 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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p.From.Reg = r
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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case ssa.OpAMD64LEAQ1, ssa.OpAMD64LEAQ2, ssa.OpAMD64LEAQ4, ssa.OpAMD64LEAQ8:
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case ssa.OpAMD64LEAQ1, ssa.OpAMD64LEAQ2, ssa.OpAMD64LEAQ4, ssa.OpAMD64LEAQ8,
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ssa.OpAMD64LEAL1, ssa.OpAMD64LEAL2, ssa.OpAMD64LEAL4, ssa.OpAMD64LEAL8,
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ssa.OpAMD64LEAW1, ssa.OpAMD64LEAW2, ssa.OpAMD64LEAW4, ssa.OpAMD64LEAW8:
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r := v.Args[0].Reg()
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i := v.Args[1].Reg()
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p := s.Prog(x86.ALEAQ)
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p := s.Prog(v.Op.Asm())
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switch v.Op {
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case ssa.OpAMD64LEAQ1:
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case ssa.OpAMD64LEAQ1, ssa.OpAMD64LEAL1, ssa.OpAMD64LEAW1:
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p.From.Scale = 1
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if i == x86.REG_SP {
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r, i = i, r
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}
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case ssa.OpAMD64LEAQ2:
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case ssa.OpAMD64LEAQ2, ssa.OpAMD64LEAL2, ssa.OpAMD64LEAW2:
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p.From.Scale = 2
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case ssa.OpAMD64LEAQ4:
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case ssa.OpAMD64LEAQ4, ssa.OpAMD64LEAL4, ssa.OpAMD64LEAW4:
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p.From.Scale = 4
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case ssa.OpAMD64LEAQ8:
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case ssa.OpAMD64LEAQ8, ssa.OpAMD64LEAL8, ssa.OpAMD64LEAW8:
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p.From.Scale = 8
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}
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p.From.Type = obj.TYPE_MEM
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@ -544,7 +546,7 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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gc.AddAux(&p.From, v)
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p.To.Type = obj.TYPE_REG
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p.To.Reg = v.Reg()
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case ssa.OpAMD64LEAQ, ssa.OpAMD64LEAL:
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case ssa.OpAMD64LEAQ, ssa.OpAMD64LEAL, ssa.OpAMD64LEAW:
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p := s.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_MEM
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p.From.Reg = v.Args[0].Reg()
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@ -486,13 +486,21 @@ func init() {
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{name: "PXOR", argLength: 2, reg: fp21, asm: "PXOR", commutative: true, resultInArg0: true}, // exclusive or, applied to X regs for float negation.
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{name: "LEAQ", argLength: 1, reg: gp11sb, asm: "LEAQ", aux: "SymOff", rematerializeable: true, symEffect: "Addr"}, // arg0 + auxint + offset encoded in aux
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{name: "LEAQ1", argLength: 2, reg: gp21sb, commutative: true, aux: "SymOff", symEffect: "Addr"}, // arg0 + arg1 + auxint + aux
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{name: "LEAQ2", argLength: 2, reg: gp21sb, aux: "SymOff", symEffect: "Addr"}, // arg0 + 2*arg1 + auxint + aux
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{name: "LEAQ4", argLength: 2, reg: gp21sb, aux: "SymOff", symEffect: "Addr"}, // arg0 + 4*arg1 + auxint + aux
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{name: "LEAQ8", argLength: 2, reg: gp21sb, aux: "SymOff", symEffect: "Addr"}, // arg0 + 8*arg1 + auxint + aux
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// Note: LEAQ{1,2,4,8} must not have OpSB as either argument.
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{name: "LEAL", argLength: 1, reg: gp11sb, asm: "LEAL", aux: "SymOff", rematerializeable: true, symEffect: "Addr"}, // arg0 + auxint + offset encoded in aux
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{name: "LEAW", argLength: 1, reg: gp11sb, asm: "LEAW", aux: "SymOff", rematerializeable: true, symEffect: "Addr"}, // arg0 + auxint + offset encoded in aux
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{name: "LEAQ1", argLength: 2, reg: gp21sb, asm: "LEAQ", commutative: true, aux: "SymOff", symEffect: "Addr"}, // arg0 + arg1 + auxint + aux
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{name: "LEAL1", argLength: 2, reg: gp21sb, asm: "LEAL", commutative: true, aux: "SymOff", symEffect: "Addr"}, // arg0 + arg1 + auxint + aux
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{name: "LEAW1", argLength: 2, reg: gp21sb, asm: "LEAW", commutative: true, aux: "SymOff", symEffect: "Addr"}, // arg0 + arg1 + auxint + aux
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{name: "LEAQ2", argLength: 2, reg: gp21sb, asm: "LEAQ", aux: "SymOff", symEffect: "Addr"}, // arg0 + 2*arg1 + auxint + aux
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{name: "LEAL2", argLength: 2, reg: gp21sb, asm: "LEAL", aux: "SymOff", symEffect: "Addr"}, // arg0 + 2*arg1 + auxint + aux
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{name: "LEAW2", argLength: 2, reg: gp21sb, asm: "LEAW", aux: "SymOff", symEffect: "Addr"}, // arg0 + 2*arg1 + auxint + aux
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{name: "LEAQ4", argLength: 2, reg: gp21sb, asm: "LEAQ", aux: "SymOff", symEffect: "Addr"}, // arg0 + 4*arg1 + auxint + aux
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{name: "LEAL4", argLength: 2, reg: gp21sb, asm: "LEAL", aux: "SymOff", symEffect: "Addr"}, // arg0 + 4*arg1 + auxint + aux
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{name: "LEAW4", argLength: 2, reg: gp21sb, asm: "LEAW", aux: "SymOff", symEffect: "Addr"}, // arg0 + 4*arg1 + auxint + aux
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{name: "LEAQ8", argLength: 2, reg: gp21sb, asm: "LEAQ", aux: "SymOff", symEffect: "Addr"}, // arg0 + 8*arg1 + auxint + aux
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{name: "LEAL8", argLength: 2, reg: gp21sb, asm: "LEAL", aux: "SymOff", symEffect: "Addr"}, // arg0 + 8*arg1 + auxint + aux
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{name: "LEAW8", argLength: 2, reg: gp21sb, asm: "LEAW", aux: "SymOff", symEffect: "Addr"}, // arg0 + 8*arg1 + auxint + aux
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// Note: LEAx{1,2,4,8} must not have OpSB as either argument.
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// auxint+aux == add auxint and the offset of the symbol in aux (if any) to the effective address
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{name: "MOVBload", argLength: 2, reg: gpload, asm: "MOVBLZX", aux: "SymOff", typ: "UInt8", faultOnNilArg0: true, symEffect: "Read"}, // load byte from arg0+auxint+aux. arg1=mem. Zero extend.
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@ -681,11 +681,20 @@ const (
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OpAMD64MOVLf2i
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OpAMD64PXOR
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OpAMD64LEAQ
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OpAMD64LEAQ1
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OpAMD64LEAQ2
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OpAMD64LEAQ4
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OpAMD64LEAQ8
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OpAMD64LEAL
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OpAMD64LEAW
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OpAMD64LEAQ1
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OpAMD64LEAL1
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OpAMD64LEAW1
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OpAMD64LEAQ2
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OpAMD64LEAL2
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OpAMD64LEAW2
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OpAMD64LEAQ4
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OpAMD64LEAL4
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OpAMD64LEAW4
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OpAMD64LEAQ8
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OpAMD64LEAL8
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OpAMD64LEAW8
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OpAMD64MOVBload
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OpAMD64MOVBQSXload
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OpAMD64MOVWload
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@ -8585,12 +8594,79 @@ var opcodeTable = [...]opInfo{
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},
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},
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},
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{
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name: "LEAL",
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auxType: auxSymOff,
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argLen: 1,
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rematerializeable: true,
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symEffect: SymAddr,
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asm: x86.ALEAL,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
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},
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outputs: []outputInfo{
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{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
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},
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},
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},
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{
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name: "LEAW",
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auxType: auxSymOff,
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argLen: 1,
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rematerializeable: true,
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symEffect: SymAddr,
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asm: x86.ALEAW,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
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},
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outputs: []outputInfo{
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{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
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},
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},
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},
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{
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name: "LEAQ1",
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auxType: auxSymOff,
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argLen: 2,
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commutative: true,
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symEffect: SymAddr,
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asm: x86.ALEAQ,
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reg: regInfo{
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inputs: []inputInfo{
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{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
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{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
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},
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outputs: []outputInfo{
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{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
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},
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},
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},
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{
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name: "LEAL1",
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auxType: auxSymOff,
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argLen: 2,
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commutative: true,
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symEffect: SymAddr,
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asm: x86.ALEAL,
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reg: regInfo{
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inputs: []inputInfo{
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{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
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{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
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},
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outputs: []outputInfo{
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{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
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},
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},
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},
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{
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name: "LEAW1",
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auxType: auxSymOff,
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argLen: 2,
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commutative: true,
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symEffect: SymAddr,
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asm: x86.ALEAW,
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reg: regInfo{
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inputs: []inputInfo{
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{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
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@ -8606,6 +8682,39 @@ var opcodeTable = [...]opInfo{
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auxType: auxSymOff,
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argLen: 2,
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symEffect: SymAddr,
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asm: x86.ALEAQ,
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reg: regInfo{
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inputs: []inputInfo{
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{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
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{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
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},
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outputs: []outputInfo{
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{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
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},
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},
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},
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{
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name: "LEAL2",
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auxType: auxSymOff,
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argLen: 2,
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symEffect: SymAddr,
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asm: x86.ALEAL,
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reg: regInfo{
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inputs: []inputInfo{
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{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
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{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
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},
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outputs: []outputInfo{
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{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
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},
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},
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},
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{
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name: "LEAW2",
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auxType: auxSymOff,
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argLen: 2,
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symEffect: SymAddr,
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asm: x86.ALEAW,
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reg: regInfo{
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inputs: []inputInfo{
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{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
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@ -8621,6 +8730,39 @@ var opcodeTable = [...]opInfo{
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auxType: auxSymOff,
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argLen: 2,
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symEffect: SymAddr,
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asm: x86.ALEAQ,
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reg: regInfo{
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inputs: []inputInfo{
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{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
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{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
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},
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outputs: []outputInfo{
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{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
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},
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},
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},
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{
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name: "LEAL4",
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auxType: auxSymOff,
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argLen: 2,
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symEffect: SymAddr,
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asm: x86.ALEAL,
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reg: regInfo{
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inputs: []inputInfo{
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{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
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{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
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},
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outputs: []outputInfo{
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{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
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},
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},
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},
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{
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name: "LEAW4",
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auxType: auxSymOff,
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argLen: 2,
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symEffect: SymAddr,
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asm: x86.ALEAW,
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reg: regInfo{
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inputs: []inputInfo{
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{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
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@ -8636,6 +8778,7 @@ var opcodeTable = [...]opInfo{
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auxType: auxSymOff,
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argLen: 2,
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symEffect: SymAddr,
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asm: x86.ALEAQ,
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reg: regInfo{
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inputs: []inputInfo{
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{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
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@ -8647,14 +8790,30 @@ var opcodeTable = [...]opInfo{
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},
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},
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{
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name: "LEAL",
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auxType: auxSymOff,
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argLen: 1,
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rematerializeable: true,
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symEffect: SymAddr,
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asm: x86.ALEAL,
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name: "LEAL8",
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auxType: auxSymOff,
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argLen: 2,
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symEffect: SymAddr,
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asm: x86.ALEAL,
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reg: regInfo{
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inputs: []inputInfo{
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{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
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{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
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},
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outputs: []outputInfo{
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{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
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},
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},
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},
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{
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name: "LEAW8",
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auxType: auxSymOff,
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argLen: 2,
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symEffect: SymAddr,
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asm: x86.ALEAW,
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reg: regInfo{
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inputs: []inputInfo{
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{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
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{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
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},
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outputs: []outputInfo{
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