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runtime: slightly clean up softfloat code

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Removes the remains of the old C based stepflt implementation.
Also removed goto usage.

Change-Id: Ida4742c49000fae4fea4649f28afde630ce4c577
Reviewed-on: https://go-review.googlesource.com/9600
Reviewed-by: Russ Cox <rsc@golang.org>
This commit is contained in:
Shenghou Ma 2015-05-01 03:55:17 -04:00 committed by Russ Cox
parent 32fddadd98
commit 21a4c93166
2 changed files with 62 additions and 111 deletions
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13
src/runtime/softfloat64.go
View File

@ -483,16 +483,3 @@ again2:
return q1*b + q0, (un21*b + un0 - q0*v) >> s return q1*b + q0, (un21*b + un0 - q0*v) >> s
} }
// callable from C
func fadd64c(f, g uint64, ret *uint64) { *ret = fadd64(f, g) }
func fsub64c(f, g uint64, ret *uint64) { *ret = fsub64(f, g) }
func fmul64c(f, g uint64, ret *uint64) { *ret = fmul64(f, g) }
func fdiv64c(f, g uint64, ret *uint64) { *ret = fdiv64(f, g) }
func fneg64c(f uint64, ret *uint64) { *ret = fneg64(f) }
func f32to64c(f uint32, ret *uint64) { *ret = f32to64(f) }
func f64to32c(f uint64, ret *uint32) { *ret = f64to32(f) }
func fcmp64c(f, g uint64, ret *int32, retnan *bool) { *ret, *retnan = fcmp64(f, g) }
func fintto64c(val int64, ret *uint64) { *ret = fintto64(val) }
func f64tointc(f uint64, ret *int64, retok *bool) { *ret, *retok = f64toint(f) }

160
src/runtime/softfloat_arm.go
View File

@ -77,13 +77,7 @@ const _FAULT = 0x80000000 // impossible PC offset
// returns number of words that the fp instruction // returns number of words that the fp instruction
// is occupying, 0 if next instruction isn't float. // is occupying, 0 if next instruction isn't float.
func stepflt(pc *uint32, regs *[15]uint32) uint32 { func stepflt(pc *uint32, regs *[15]uint32) uint32 {
var ( var i, opc, regd, regm, regn, cpsr uint32
i, opc, regd, regm, regn, cpsr uint32
cmp, delta int32
uval uint64
sval int64
nan, ok bool
)
// m is locked in vlop_arm.s, so g.m cannot change during this function call, // m is locked in vlop_arm.s, so g.m cannot change during this function call,
// so caching it in a local variable is safe. // so caching it in a local variable is safe.
@ -187,7 +181,7 @@ execute:
// can happen in the middle of floating point // can happen in the middle of floating point
// if the linker decides it is time to lay down // if the linker decides it is time to lay down
// a sequence of instruction stream constants. // a sequence of instruction stream constants.
delta = int32(i&0xffffff) << 8 >> 8 // sign extend delta := int32(i&0xffffff) << 8 >> 8 // sign extend
if fptrace > 0 { if fptrace > 0 {
print("*** cpu PC += ", hex((delta+2)*4), "\n") print("*** cpu PC += ", hex((delta+2)*4), "\n")
@ -195,17 +189,12 @@ execute:
return uint32(delta + 2) return uint32(delta + 2)
} }
goto stage1 // load/store regn is cpureg, regm is 8bit offset
stage1: // load/store regn is cpureg, regm is 8bit offset
regd = i >> 12 & 0xf regd = i >> 12 & 0xf
regn = i >> 16 & 0xf regn = i >> 16 & 0xf
regm = i & 0xff << 2 // PLUS or MINUS ?? regm = i & 0xff << 2 // PLUS or MINUS ??
switch i & 0xfff00f00 { switch i & 0xfff00f00 {
default:
goto stage2
case 0xed900a00: // single load case 0xed900a00: // single load
uaddr := uintptr(regs[regn] + regm) uaddr := uintptr(regs[regn] + regm)
if uaddr < 4096 { if uaddr < 4096 {
@ -220,7 +209,7 @@ stage1: // load/store regn is cpureg, regm is 8bit offset
if fptrace > 0 { if fptrace > 0 {
print("*** load F[", regd, "] = ", hex(m.freglo[regd]), "\n") print("*** load F[", regd, "] = ", hex(m.freglo[regd]), "\n")
} }
break return 1
case 0xed900b00: // double load case 0xed900b00: // double load
uaddr := uintptr(regs[regn] + regm) uaddr := uintptr(regs[regn] + regm)
@ -237,7 +226,7 @@ stage1: // load/store regn is cpureg, regm is 8bit offset
if fptrace > 0 { if fptrace > 0 {
print("*** load D[", regd, "] = ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n") print("*** load D[", regd, "] = ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
} }
break return 1
case 0xed800a00: // single store case 0xed800a00: // single store
uaddr := uintptr(regs[regn] + regm) uaddr := uintptr(regs[regn] + regm)
@ -253,7 +242,7 @@ stage1: // load/store regn is cpureg, regm is 8bit offset
if fptrace > 0 { if fptrace > 0 {
print("*** *(", addr, ") = ", hex(addr[0]), "\n") print("*** *(", addr, ") = ", hex(addr[0]), "\n")
} }
break return 1
case 0xed800b00: // double store case 0xed800b00: // double store
uaddr := uintptr(regs[regn] + regm) uaddr := uintptr(regs[regn] + regm)
@ -270,16 +259,12 @@ stage1: // load/store regn is cpureg, regm is 8bit offset
if fptrace > 0 { if fptrace > 0 {
print("*** *(", addr, ") = ", hex(addr[1]), "-", hex(addr[0]), "\n") print("*** *(", addr, ") = ", hex(addr[1]), "-", hex(addr[0]), "\n")
} }
break return 1
} }
return 1
stage2: // regd, regm, regn are 4bit variables // regd, regm, regn are 4bit variables
regm = i >> 0 & 0xf regm = i >> 0 & 0xf
switch i & 0xfff00ff0 { switch i & 0xfff00ff0 {
default:
goto stage3
case 0xf3000110: // veor case 0xf3000110: // veor
m.freglo[regd] = m.freglo[regm] ^ m.freglo[regn] m.freglo[regd] = m.freglo[regm] ^ m.freglo[regn]
m.freghi[regd] = m.freghi[regm] ^ m.freghi[regn] m.freghi[regd] = m.freghi[regm] ^ m.freghi[regn]
@ -287,7 +272,7 @@ stage2: // regd, regm, regn are 4bit variables
if fptrace > 0 { if fptrace > 0 {
print("*** veor D[", regd, "] = ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n") print("*** veor D[", regd, "] = ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
} }
break return 1
case 0xeeb00b00: // D[regd] = const(regn,regm) case 0xeeb00b00: // D[regd] = const(regn,regm)
regn = regn<<4 | regm regn = regn<<4 | regm
@ -305,7 +290,7 @@ stage2: // regd, regm, regn are 4bit variables
if fptrace > 0 { if fptrace > 0 {
print("*** immed D[", regd, "] = ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n") print("*** immed D[", regd, "] = ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
} }
break return 1
case 0xeeb00a00: // F[regd] = const(regn,regm) case 0xeeb00a00: // F[regd] = const(regn,regm)
regn = regn<<4 | regm regn = regn<<4 | regm
@ -322,79 +307,71 @@ stage2: // regd, regm, regn are 4bit variables
if fptrace > 0 { if fptrace > 0 {
print("*** immed D[", regd, "] = ", hex(m.freglo[regd]), "\n") print("*** immed D[", regd, "] = ", hex(m.freglo[regd]), "\n")
} }
break return 1
case 0xee300b00: // D[regd] = D[regn]+D[regm] case 0xee300b00: // D[regd] = D[regn]+D[regm]
fadd64c(fgetd(regn), fgetd(regm), &uval) fputd(regd, fadd64(fgetd(regn), fgetd(regm)))
fputd(regd, uval)
if fptrace > 0 { if fptrace > 0 {
print("*** add D[", regd, "] = D[", regn, "]+D[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n") print("*** add D[", regd, "] = D[", regn, "]+D[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
} }
break return 1
case 0xee300a00: // F[regd] = F[regn]+F[regm] case 0xee300a00: // F[regd] = F[regn]+F[regm]
fadd64c(f32to64(m.freglo[regn]), f32to64(m.freglo[regm]), &uval) m.freglo[regd] = f64to32(fadd64(f32to64(m.freglo[regn]), f32to64(m.freglo[regm])))
m.freglo[regd] = f64to32(uval)
if fptrace > 0 { if fptrace > 0 {
print("*** add F[", regd, "] = F[", regn, "]+F[", regm, "] ", hex(m.freglo[regd]), "\n") print("*** add F[", regd, "] = F[", regn, "]+F[", regm, "] ", hex(m.freglo[regd]), "\n")
} }
break return 1
case 0xee300b40: // D[regd] = D[regn]-D[regm] case 0xee300b40: // D[regd] = D[regn]-D[regm]
fsub64c(fgetd(regn), fgetd(regm), &uval) fputd(regd, fsub64(fgetd(regn), fgetd(regm)))
fputd(regd, uval)
if fptrace > 0 { if fptrace > 0 {
print("*** sub D[", regd, "] = D[", regn, "]-D[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n") print("*** sub D[", regd, "] = D[", regn, "]-D[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
} }
break return 1
case 0xee300a40: // F[regd] = F[regn]-F[regm] case 0xee300a40: // F[regd] = F[regn]-F[regm]
fsub64c(f32to64(m.freglo[regn]), f32to64(m.freglo[regm]), &uval) m.freglo[regd] = f64to32(fsub64(f32to64(m.freglo[regn]), f32to64(m.freglo[regm])))
m.freglo[regd] = f64to32(uval)
if fptrace > 0 { if fptrace > 0 {
print("*** sub F[", regd, "] = F[", regn, "]-F[", regm, "] ", hex(m.freglo[regd]), "\n") print("*** sub F[", regd, "] = F[", regn, "]-F[", regm, "] ", hex(m.freglo[regd]), "\n")
} }
break return 1
case 0xee200b00: // D[regd] = D[regn]*D[regm] case 0xee200b00: // D[regd] = D[regn]*D[regm]
fmul64c(fgetd(regn), fgetd(regm), &uval) fputd(regd, fmul64(fgetd(regn), fgetd(regm)))
fputd(regd, uval)
if fptrace > 0 { if fptrace > 0 {
print("*** mul D[", regd, "] = D[", regn, "]*D[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n") print("*** mul D[", regd, "] = D[", regn, "]*D[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
} }
break return 1
case 0xee200a00: // F[regd] = F[regn]*F[regm] case 0xee200a00: // F[regd] = F[regn]*F[regm]
fmul64c(f32to64(m.freglo[regn]), f32to64(m.freglo[regm]), &uval) m.freglo[regd] = f64to32(fmul64(f32to64(m.freglo[regn]), f32to64(m.freglo[regm])))
m.freglo[regd] = f64to32(uval)
if fptrace > 0 { if fptrace > 0 {
print("*** mul F[", regd, "] = F[", regn, "]*F[", regm, "] ", hex(m.freglo[regd]), "\n") print("*** mul F[", regd, "] = F[", regn, "]*F[", regm, "] ", hex(m.freglo[regd]), "\n")
} }
break return 1
case 0xee800b00: // D[regd] = D[regn]/D[regm] case 0xee800b00: // D[regd] = D[regn]/D[regm]
fdiv64c(fgetd(regn), fgetd(regm), &uval) fputd(regd, fdiv64(fgetd(regn), fgetd(regm)))
fputd(regd, uval)
if fptrace > 0 { if fptrace > 0 {
print("*** div D[", regd, "] = D[", regn, "]/D[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n") print("*** div D[", regd, "] = D[", regn, "]/D[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
} }
break return 1
case 0xee800a00: // F[regd] = F[regn]/F[regm] case 0xee800a00: // F[regd] = F[regn]/F[regm]
fdiv64c(f32to64(m.freglo[regn]), f32to64(m.freglo[regm]), &uval) m.freglo[regd] = f64to32(fdiv64(f32to64(m.freglo[regn]), f32to64(m.freglo[regm])))
m.freglo[regd] = f64to32(uval)
if fptrace > 0 { if fptrace > 0 {
print("*** div F[", regd, "] = F[", regn, "]/F[", regm, "] ", hex(m.freglo[regd]), "\n") print("*** div F[", regd, "] = F[", regn, "]/F[", regm, "] ", hex(m.freglo[regd]), "\n")
} }
break return 1
case 0xee000b10: // S[regn] = R[regd] (MOVW) (regm ignored) case 0xee000b10: // S[regn] = R[regd] (MOVW) (regm ignored)
m.freglo[regn] = regs[regd] m.freglo[regn] = regs[regd]
@ -402,7 +379,7 @@ stage2: // regd, regm, regn are 4bit variables
if fptrace > 0 { if fptrace > 0 {
print("*** cpy S[", regn, "] = R[", regd, "] ", hex(m.freglo[regn]), "\n") print("*** cpy S[", regn, "] = R[", regd, "] ", hex(m.freglo[regn]), "\n")
} }
break return 1
case 0xee100b10: // R[regd] = S[regn] (MOVW) (regm ignored) case 0xee100b10: // R[regd] = S[regn] (MOVW) (regm ignored)
regs[regd] = m.freglo[regn] regs[regd] = m.freglo[regn]
@ -410,22 +387,18 @@ stage2: // regd, regm, regn are 4bit variables
if fptrace > 0 { if fptrace > 0 {
print("*** cpy R[", regd, "] = S[", regn, "] ", hex(regs[regd]), "\n") print("*** cpy R[", regd, "] = S[", regn, "] ", hex(regs[regd]), "\n")
} }
break return 1
} }
return 1
stage3: // regd, regm are 4bit variables // regd, regm are 4bit variables
switch i & 0xffff0ff0 { switch i & 0xffff0ff0 {
default:
goto done
case 0xeeb00a40: // F[regd] = F[regm] (MOVF) case 0xeeb00a40: // F[regd] = F[regm] (MOVF)
m.freglo[regd] = m.freglo[regm] m.freglo[regd] = m.freglo[regm]
if fptrace > 0 { if fptrace > 0 {
print("*** F[", regd, "] = F[", regm, "] ", hex(m.freglo[regd]), "\n") print("*** F[", regd, "] = F[", regm, "] ", hex(m.freglo[regd]), "\n")
} }
break return 1
case 0xeeb00b40: // D[regd] = D[regm] (MOVD) case 0xeeb00b40: // D[regd] = D[regm] (MOVD)
m.freglo[regd] = m.freglo[regm] m.freglo[regd] = m.freglo[regm]
@ -434,7 +407,7 @@ stage3: // regd, regm are 4bit variables
if fptrace > 0 { if fptrace > 0 {
print("*** D[", regd, "] = D[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n") print("*** D[", regd, "] = D[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
} }
break return 1
case 0xeeb10bc0: // D[regd] = sqrt D[regm] case 0xeeb10bc0: // D[regd] = sqrt D[regm]
fputd(regd, sqrt(fgetd(regm))) fputd(regd, sqrt(fgetd(regm)))
@ -442,7 +415,7 @@ stage3: // regd, regm are 4bit variables
if fptrace > 0 { if fptrace > 0 {
print("*** D[", regd, "] = sqrt D[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n") print("*** D[", regd, "] = sqrt D[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
} }
break return 1
case 0xeeb00bc0: // D[regd] = abs D[regm] case 0xeeb00bc0: // D[regd] = abs D[regm]
m.freglo[regd] = m.freglo[regm] m.freglo[regd] = m.freglo[regm]
@ -451,7 +424,7 @@ stage3: // regd, regm are 4bit variables
if fptrace > 0 { if fptrace > 0 {
print("*** D[", regd, "] = abs D[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n") print("*** D[", regd, "] = abs D[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
} }
break return 1
case 0xeeb00ac0: // F[regd] = abs F[regm] case 0xeeb00ac0: // F[regd] = abs F[regm]
m.freglo[regd] = m.freglo[regm] & (1<<31 - 1) m.freglo[regd] = m.freglo[regm] & (1<<31 - 1)
@ -459,25 +432,25 @@ stage3: // regd, regm are 4bit variables
if fptrace > 0 { if fptrace > 0 {
print("*** F[", regd, "] = abs F[", regm, "] ", hex(m.freglo[regd]), "\n") print("*** F[", regd, "] = abs F[", regm, "] ", hex(m.freglo[regd]), "\n")
} }
break return 1
case 0xeeb40bc0: // D[regd] :: D[regm] (CMPD) case 0xeeb40bc0: // D[regd] :: D[regm] (CMPD)
fcmp64c(fgetd(regd), fgetd(regm), &cmp, &nan) cmp, nan := fcmp64(fgetd(regd), fgetd(regm))
m.fflag = fstatus(nan, cmp) m.fflag = fstatus(nan, cmp)
if fptrace > 0 { if fptrace > 0 {
print("*** cmp D[", regd, "]::D[", regm, "] ", hex(m.fflag), "\n") print("*** cmp D[", regd, "]::D[", regm, "] ", hex(m.fflag), "\n")
} }
break return 1
case 0xeeb40ac0: // F[regd] :: F[regm] (CMPF) case 0xeeb40ac0: // F[regd] :: F[regm] (CMPF)
fcmp64c(f32to64(m.freglo[regd]), f32to64(m.freglo[regm]), &cmp, &nan) cmp, nan := fcmp64(f32to64(m.freglo[regd]), f32to64(m.freglo[regm]))
m.fflag = fstatus(nan, cmp) m.fflag = fstatus(nan, cmp)
if fptrace > 0 { if fptrace > 0 {
print("*** cmp F[", regd, "]::F[", regm, "] ", hex(m.fflag), "\n") print("*** cmp F[", regd, "]::F[", regm, "] ", hex(m.fflag), "\n")
} }
break return 1
case 0xeeb70ac0: // D[regd] = F[regm] (MOVFD) case 0xeeb70ac0: // D[regd] = F[regm] (MOVFD)
fputd(regd, f32to64(m.freglo[regm])) fputd(regd, f32to64(m.freglo[regm]))
@ -485,7 +458,7 @@ stage3: // regd, regm are 4bit variables
if fptrace > 0 { if fptrace > 0 {
print("*** f2d D[", regd, "]=F[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n") print("*** f2d D[", regd, "]=F[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
} }
break return 1
case 0xeeb70bc0: // F[regd] = D[regm] (MOVDF) case 0xeeb70bc0: // F[regd] = D[regm] (MOVDF)
m.freglo[regd] = f64to32(fgetd(regm)) m.freglo[regd] = f64to32(fgetd(regm))
@ -493,10 +466,10 @@ stage3: // regd, regm are 4bit variables
if fptrace > 0 { if fptrace > 0 {
print("*** d2f F[", regd, "]=D[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n") print("*** d2f F[", regd, "]=D[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
} }
break return 1
case 0xeebd0ac0: // S[regd] = F[regm] (MOVFW) case 0xeebd0ac0: // S[regd] = F[regm] (MOVFW)
f64tointc(f32to64(m.freglo[regm]), &sval, &ok) sval, ok := f64toint(f32to64(m.freglo[regm]))
if !ok || int64(int32(sval)) != sval { if !ok || int64(int32(sval)) != sval {
sval = 0 sval = 0
} }
@ -504,10 +477,10 @@ stage3: // regd, regm are 4bit variables
if fptrace > 0 { if fptrace > 0 {
print("*** fix S[", regd, "]=F[", regm, "] ", hex(m.freglo[regd]), "\n") print("*** fix S[", regd, "]=F[", regm, "] ", hex(m.freglo[regd]), "\n")
} }
break return 1
case 0xeebc0ac0: // S[regd] = F[regm] (MOVFW.U) case 0xeebc0ac0: // S[regd] = F[regm] (MOVFW.U)
f64tointc(f32to64(m.freglo[regm]), &sval, &ok) sval, ok := f64toint(f32to64(m.freglo[regm]))
if !ok || int64(uint32(sval)) != sval { if !ok || int64(uint32(sval)) != sval {
sval = 0 sval = 0
} }
@ -516,10 +489,10 @@ stage3: // regd, regm are 4bit variables
if fptrace > 0 { if fptrace > 0 {
print("*** fix unsigned S[", regd, "]=F[", regm, "] ", hex(m.freglo[regd]), "\n") print("*** fix unsigned S[", regd, "]=F[", regm, "] ", hex(m.freglo[regd]), "\n")
} }
break return 1
case 0xeebd0bc0: // S[regd] = D[regm] (MOVDW) case 0xeebd0bc0: // S[regd] = D[regm] (MOVDW)
f64tointc(fgetd(regm), &sval, &ok) sval, ok := f64toint(fgetd(regm))
if !ok || int64(int32(sval)) != sval { if !ok || int64(int32(sval)) != sval {
sval = 0 sval = 0
} }
@ -528,10 +501,10 @@ stage3: // regd, regm are 4bit variables
if fptrace > 0 { if fptrace > 0 {
print("*** fix S[", regd, "]=D[", regm, "] ", hex(m.freglo[regd]), "\n") print("*** fix S[", regd, "]=D[", regm, "] ", hex(m.freglo[regd]), "\n")
} }
break return 1
case 0xeebc0bc0: // S[regd] = D[regm] (MOVDW.U) case 0xeebc0bc0: // S[regd] = D[regm] (MOVDW.U)
f64tointc(fgetd(regm), &sval, &ok) sval, ok := f64toint(fgetd(regm))
if !ok || int64(uint32(sval)) != sval { if !ok || int64(uint32(sval)) != sval {
sval = 0 sval = 0
} }
@ -540,63 +513,54 @@ stage3: // regd, regm are 4bit variables
if fptrace > 0 { if fptrace > 0 {
print("*** fix unsigned S[", regd, "]=D[", regm, "] ", hex(m.freglo[regd]), "\n") print("*** fix unsigned S[", regd, "]=D[", regm, "] ", hex(m.freglo[regd]), "\n")
} }
break return 1
case 0xeeb80ac0: // D[regd] = S[regm] (MOVWF) case 0xeeb80ac0: // D[regd] = S[regm] (MOVWF)
cmp = int32(m.freglo[regm]) cmp := int32(m.freglo[regm])
if cmp < 0 { if cmp < 0 {
fintto64c(int64(-cmp), &uval) fputf(regd, f64to32(fintto64(int64(-cmp))))
fputf(regd, f64to32(uval))
m.freglo[regd] ^= 0x80000000 m.freglo[regd] ^= 0x80000000
} else { } else {
fintto64c(int64(cmp), &uval) fputf(regd, f64to32(fintto64(int64(cmp))))
fputf(regd, f64to32(uval))
} }
if fptrace > 0 { if fptrace > 0 {
print("*** float D[", regd, "]=S[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n") print("*** float D[", regd, "]=S[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
} }
break return 1
case 0xeeb80a40: // D[regd] = S[regm] (MOVWF.U) case 0xeeb80a40: // D[regd] = S[regm] (MOVWF.U)
fintto64c(int64(m.freglo[regm]), &uval) fputf(regd, f64to32(fintto64(int64(m.freglo[regm]))))
fputf(regd, f64to32(uval))
if fptrace > 0 { if fptrace > 0 {
print("*** float unsigned D[", regd, "]=S[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n") print("*** float unsigned D[", regd, "]=S[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
} }
break return 1
case 0xeeb80bc0: // D[regd] = S[regm] (MOVWD) case 0xeeb80bc0: // D[regd] = S[regm] (MOVWD)
cmp = int32(m.freglo[regm]) cmp := int32(m.freglo[regm])
if cmp < 0 { if cmp < 0 {
fintto64c(int64(-cmp), &uval) fputd(regd, fintto64(int64(-cmp)))
fputd(regd, uval)
m.freghi[regd] ^= 0x80000000 m.freghi[regd] ^= 0x80000000
} else { } else {
fintto64c(int64(cmp), &uval) fputd(regd, fintto64(int64(cmp)))
fputd(regd, uval)
} }
if fptrace > 0 { if fptrace > 0 {
print("*** float D[", regd, "]=S[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n") print("*** float D[", regd, "]=S[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
} }
break return 1
case 0xeeb80b40: // D[regd] = S[regm] (MOVWD.U) case 0xeeb80b40: // D[regd] = S[regm] (MOVWD.U)
fintto64c(int64(m.freglo[regm]), &uval) fputd(regd, fintto64(int64(m.freglo[regm])))
fputd(regd, uval)
if fptrace > 0 { if fptrace > 0 {
print("*** float unsigned D[", regd, "]=S[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n") print("*** float unsigned D[", regd, "]=S[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
} }
break return 1
} }
return 1
done: if i&0xff000000 == 0xee000000 || i&0xff000000 == 0xed000000 {
if i&0xff000000 == 0xee000000 ||
i&0xff000000 == 0xed000000 {
print("stepflt ", pc, " ", hex(i), "\n") print("stepflt ", pc, " ", hex(i), "\n")
fabort() fabort()
} }