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https://github.com/golang/go
synced 2024-11-23 05:30:07 -07:00
runtime: slightly clean up softfloat code
Removes the remains of the old C based stepflt implementation. Also removed goto usage. Change-Id: Ida4742c49000fae4fea4649f28afde630ce4c577 Reviewed-on: https://go-review.googlesource.com/9600 Reviewed-by: Russ Cox <rsc@golang.org>
This commit is contained in:
Shenghou Ma
Russ Cox
parent
32fddadd98
commit
21a4c93166
@ -483,16 +483,3 @@ again2:
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return q1*b + q0, (un21*b + un0 - q0*v) >> s
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}
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// callable from C
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func fadd64c(f, g uint64, ret *uint64) { *ret = fadd64(f, g) }
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func fsub64c(f, g uint64, ret *uint64) { *ret = fsub64(f, g) }
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func fmul64c(f, g uint64, ret *uint64) { *ret = fmul64(f, g) }
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func fdiv64c(f, g uint64, ret *uint64) { *ret = fdiv64(f, g) }
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func fneg64c(f uint64, ret *uint64) { *ret = fneg64(f) }
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func f32to64c(f uint32, ret *uint64) { *ret = f32to64(f) }
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func f64to32c(f uint64, ret *uint32) { *ret = f64to32(f) }
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func fcmp64c(f, g uint64, ret *int32, retnan *bool) { *ret, *retnan = fcmp64(f, g) }
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func fintto64c(val int64, ret *uint64) { *ret = fintto64(val) }
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func f64tointc(f uint64, ret *int64, retok *bool) { *ret, *retok = f64toint(f) }
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@ -77,13 +77,7 @@ const _FAULT = 0x80000000 // impossible PC offset
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// returns number of words that the fp instruction
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// is occupying, 0 if next instruction isn't float.
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func stepflt(pc *uint32, regs *[15]uint32) uint32 {
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var (
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i, opc, regd, regm, regn, cpsr uint32
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cmp, delta int32
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uval uint64
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sval int64
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nan, ok bool
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)
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var i, opc, regd, regm, regn, cpsr uint32
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// m is locked in vlop_arm.s, so g.m cannot change during this function call,
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// so caching it in a local variable is safe.
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@ -187,7 +181,7 @@ execute:
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// can happen in the middle of floating point
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// if the linker decides it is time to lay down
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// a sequence of instruction stream constants.
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delta = int32(i&0xffffff) << 8 >> 8 // sign extend
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delta := int32(i&0xffffff) << 8 >> 8 // sign extend
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if fptrace > 0 {
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print("*** cpu PC += ", hex((delta+2)*4), "\n")
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@ -195,17 +189,12 @@ execute:
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return uint32(delta + 2)
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}
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goto stage1
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stage1: // load/store regn is cpureg, regm is 8bit offset
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// load/store regn is cpureg, regm is 8bit offset
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regd = i >> 12 & 0xf
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regn = i >> 16 & 0xf
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regm = i & 0xff << 2 // PLUS or MINUS ??
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switch i & 0xfff00f00 {
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default:
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goto stage2
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case 0xed900a00: // single load
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uaddr := uintptr(regs[regn] + regm)
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if uaddr < 4096 {
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@ -220,7 +209,7 @@ stage1: // load/store regn is cpureg, regm is 8bit offset
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if fptrace > 0 {
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print("*** load F[", regd, "] = ", hex(m.freglo[regd]), "\n")
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}
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break
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return 1
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case 0xed900b00: // double load
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uaddr := uintptr(regs[regn] + regm)
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@ -237,7 +226,7 @@ stage1: // load/store regn is cpureg, regm is 8bit offset
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if fptrace > 0 {
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print("*** load D[", regd, "] = ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
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}
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break
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return 1
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case 0xed800a00: // single store
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uaddr := uintptr(regs[regn] + regm)
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@ -253,7 +242,7 @@ stage1: // load/store regn is cpureg, regm is 8bit offset
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if fptrace > 0 {
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print("*** *(", addr, ") = ", hex(addr[0]), "\n")
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}
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break
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return 1
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case 0xed800b00: // double store
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uaddr := uintptr(regs[regn] + regm)
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@ -270,16 +259,12 @@ stage1: // load/store regn is cpureg, regm is 8bit offset
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if fptrace > 0 {
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print("*** *(", addr, ") = ", hex(addr[1]), "-", hex(addr[0]), "\n")
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}
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break
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return 1
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}
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return 1
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stage2: // regd, regm, regn are 4bit variables
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// regd, regm, regn are 4bit variables
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regm = i >> 0 & 0xf
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switch i & 0xfff00ff0 {
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default:
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goto stage3
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case 0xf3000110: // veor
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m.freglo[regd] = m.freglo[regm] ^ m.freglo[regn]
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m.freghi[regd] = m.freghi[regm] ^ m.freghi[regn]
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@ -287,7 +272,7 @@ stage2: // regd, regm, regn are 4bit variables
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if fptrace > 0 {
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print("*** veor D[", regd, "] = ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
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}
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break
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return 1
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case 0xeeb00b00: // D[regd] = const(regn,regm)
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regn = regn<<4 | regm
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@ -305,7 +290,7 @@ stage2: // regd, regm, regn are 4bit variables
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if fptrace > 0 {
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print("*** immed D[", regd, "] = ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
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}
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break
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return 1
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case 0xeeb00a00: // F[regd] = const(regn,regm)
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regn = regn<<4 | regm
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@ -322,79 +307,71 @@ stage2: // regd, regm, regn are 4bit variables
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if fptrace > 0 {
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print("*** immed D[", regd, "] = ", hex(m.freglo[regd]), "\n")
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}
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break
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return 1
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case 0xee300b00: // D[regd] = D[regn]+D[regm]
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fadd64c(fgetd(regn), fgetd(regm), &uval)
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fputd(regd, uval)
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fputd(regd, fadd64(fgetd(regn), fgetd(regm)))
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if fptrace > 0 {
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print("*** add D[", regd, "] = D[", regn, "]+D[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
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}
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break
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return 1
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case 0xee300a00: // F[regd] = F[regn]+F[regm]
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fadd64c(f32to64(m.freglo[regn]), f32to64(m.freglo[regm]), &uval)
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m.freglo[regd] = f64to32(uval)
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m.freglo[regd] = f64to32(fadd64(f32to64(m.freglo[regn]), f32to64(m.freglo[regm])))
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if fptrace > 0 {
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print("*** add F[", regd, "] = F[", regn, "]+F[", regm, "] ", hex(m.freglo[regd]), "\n")
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}
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break
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return 1
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case 0xee300b40: // D[regd] = D[regn]-D[regm]
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fsub64c(fgetd(regn), fgetd(regm), &uval)
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fputd(regd, uval)
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fputd(regd, fsub64(fgetd(regn), fgetd(regm)))
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if fptrace > 0 {
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print("*** sub D[", regd, "] = D[", regn, "]-D[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
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}
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break
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return 1
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case 0xee300a40: // F[regd] = F[regn]-F[regm]
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fsub64c(f32to64(m.freglo[regn]), f32to64(m.freglo[regm]), &uval)
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m.freglo[regd] = f64to32(uval)
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m.freglo[regd] = f64to32(fsub64(f32to64(m.freglo[regn]), f32to64(m.freglo[regm])))
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if fptrace > 0 {
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print("*** sub F[", regd, "] = F[", regn, "]-F[", regm, "] ", hex(m.freglo[regd]), "\n")
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}
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break
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return 1
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case 0xee200b00: // D[regd] = D[regn]*D[regm]
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fmul64c(fgetd(regn), fgetd(regm), &uval)
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fputd(regd, uval)
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fputd(regd, fmul64(fgetd(regn), fgetd(regm)))
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if fptrace > 0 {
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print("*** mul D[", regd, "] = D[", regn, "]*D[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
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}
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break
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return 1
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case 0xee200a00: // F[regd] = F[regn]*F[regm]
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fmul64c(f32to64(m.freglo[regn]), f32to64(m.freglo[regm]), &uval)
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m.freglo[regd] = f64to32(uval)
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m.freglo[regd] = f64to32(fmul64(f32to64(m.freglo[regn]), f32to64(m.freglo[regm])))
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if fptrace > 0 {
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print("*** mul F[", regd, "] = F[", regn, "]*F[", regm, "] ", hex(m.freglo[regd]), "\n")
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}
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break
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return 1
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case 0xee800b00: // D[regd] = D[regn]/D[regm]
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fdiv64c(fgetd(regn), fgetd(regm), &uval)
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fputd(regd, uval)
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fputd(regd, fdiv64(fgetd(regn), fgetd(regm)))
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if fptrace > 0 {
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print("*** div D[", regd, "] = D[", regn, "]/D[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
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}
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break
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return 1
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case 0xee800a00: // F[regd] = F[regn]/F[regm]
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fdiv64c(f32to64(m.freglo[regn]), f32to64(m.freglo[regm]), &uval)
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m.freglo[regd] = f64to32(uval)
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m.freglo[regd] = f64to32(fdiv64(f32to64(m.freglo[regn]), f32to64(m.freglo[regm])))
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if fptrace > 0 {
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print("*** div F[", regd, "] = F[", regn, "]/F[", regm, "] ", hex(m.freglo[regd]), "\n")
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}
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break
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return 1
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case 0xee000b10: // S[regn] = R[regd] (MOVW) (regm ignored)
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m.freglo[regn] = regs[regd]
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@ -402,7 +379,7 @@ stage2: // regd, regm, regn are 4bit variables
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if fptrace > 0 {
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print("*** cpy S[", regn, "] = R[", regd, "] ", hex(m.freglo[regn]), "\n")
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}
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break
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return 1
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case 0xee100b10: // R[regd] = S[regn] (MOVW) (regm ignored)
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regs[regd] = m.freglo[regn]
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@ -410,22 +387,18 @@ stage2: // regd, regm, regn are 4bit variables
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if fptrace > 0 {
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print("*** cpy R[", regd, "] = S[", regn, "] ", hex(regs[regd]), "\n")
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}
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break
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return 1
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}
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return 1
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stage3: // regd, regm are 4bit variables
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// regd, regm are 4bit variables
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switch i & 0xffff0ff0 {
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default:
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goto done
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case 0xeeb00a40: // F[regd] = F[regm] (MOVF)
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m.freglo[regd] = m.freglo[regm]
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if fptrace > 0 {
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print("*** F[", regd, "] = F[", regm, "] ", hex(m.freglo[regd]), "\n")
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}
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break
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return 1
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case 0xeeb00b40: // D[regd] = D[regm] (MOVD)
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m.freglo[regd] = m.freglo[regm]
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@ -434,7 +407,7 @@ stage3: // regd, regm are 4bit variables
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if fptrace > 0 {
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print("*** D[", regd, "] = D[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
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}
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break
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return 1
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case 0xeeb10bc0: // D[regd] = sqrt D[regm]
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fputd(regd, sqrt(fgetd(regm)))
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@ -442,7 +415,7 @@ stage3: // regd, regm are 4bit variables
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if fptrace > 0 {
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print("*** D[", regd, "] = sqrt D[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
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}
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break
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return 1
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case 0xeeb00bc0: // D[regd] = abs D[regm]
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m.freglo[regd] = m.freglo[regm]
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@ -451,7 +424,7 @@ stage3: // regd, regm are 4bit variables
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if fptrace > 0 {
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print("*** D[", regd, "] = abs D[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
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}
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break
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return 1
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case 0xeeb00ac0: // F[regd] = abs F[regm]
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m.freglo[regd] = m.freglo[regm] & (1<<31 - 1)
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@ -459,25 +432,25 @@ stage3: // regd, regm are 4bit variables
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if fptrace > 0 {
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print("*** F[", regd, "] = abs F[", regm, "] ", hex(m.freglo[regd]), "\n")
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}
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break
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return 1
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case 0xeeb40bc0: // D[regd] :: D[regm] (CMPD)
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fcmp64c(fgetd(regd), fgetd(regm), &cmp, &nan)
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cmp, nan := fcmp64(fgetd(regd), fgetd(regm))
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m.fflag = fstatus(nan, cmp)
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if fptrace > 0 {
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print("*** cmp D[", regd, "]::D[", regm, "] ", hex(m.fflag), "\n")
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}
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break
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return 1
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case 0xeeb40ac0: // F[regd] :: F[regm] (CMPF)
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fcmp64c(f32to64(m.freglo[regd]), f32to64(m.freglo[regm]), &cmp, &nan)
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cmp, nan := fcmp64(f32to64(m.freglo[regd]), f32to64(m.freglo[regm]))
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m.fflag = fstatus(nan, cmp)
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if fptrace > 0 {
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print("*** cmp F[", regd, "]::F[", regm, "] ", hex(m.fflag), "\n")
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}
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break
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return 1
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case 0xeeb70ac0: // D[regd] = F[regm] (MOVFD)
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fputd(regd, f32to64(m.freglo[regm]))
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@ -485,7 +458,7 @@ stage3: // regd, regm are 4bit variables
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if fptrace > 0 {
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print("*** f2d D[", regd, "]=F[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
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}
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break
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return 1
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case 0xeeb70bc0: // F[regd] = D[regm] (MOVDF)
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m.freglo[regd] = f64to32(fgetd(regm))
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@ -493,10 +466,10 @@ stage3: // regd, regm are 4bit variables
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if fptrace > 0 {
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print("*** d2f F[", regd, "]=D[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
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}
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break
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return 1
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case 0xeebd0ac0: // S[regd] = F[regm] (MOVFW)
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f64tointc(f32to64(m.freglo[regm]), &sval, &ok)
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sval, ok := f64toint(f32to64(m.freglo[regm]))
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if !ok || int64(int32(sval)) != sval {
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sval = 0
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}
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@ -504,10 +477,10 @@ stage3: // regd, regm are 4bit variables
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if fptrace > 0 {
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print("*** fix S[", regd, "]=F[", regm, "] ", hex(m.freglo[regd]), "\n")
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}
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break
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return 1
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case 0xeebc0ac0: // S[regd] = F[regm] (MOVFW.U)
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f64tointc(f32to64(m.freglo[regm]), &sval, &ok)
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sval, ok := f64toint(f32to64(m.freglo[regm]))
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if !ok || int64(uint32(sval)) != sval {
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sval = 0
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}
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@ -516,10 +489,10 @@ stage3: // regd, regm are 4bit variables
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if fptrace > 0 {
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print("*** fix unsigned S[", regd, "]=F[", regm, "] ", hex(m.freglo[regd]), "\n")
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}
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break
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return 1
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case 0xeebd0bc0: // S[regd] = D[regm] (MOVDW)
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f64tointc(fgetd(regm), &sval, &ok)
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sval, ok := f64toint(fgetd(regm))
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if !ok || int64(int32(sval)) != sval {
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sval = 0
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}
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@ -528,10 +501,10 @@ stage3: // regd, regm are 4bit variables
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if fptrace > 0 {
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print("*** fix S[", regd, "]=D[", regm, "] ", hex(m.freglo[regd]), "\n")
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}
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break
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return 1
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case 0xeebc0bc0: // S[regd] = D[regm] (MOVDW.U)
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f64tointc(fgetd(regm), &sval, &ok)
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sval, ok := f64toint(fgetd(regm))
|
||||
if !ok || int64(uint32(sval)) != sval {
|
||||
sval = 0
|
||||
}
|
||||
@ -540,63 +513,54 @@ stage3: // regd, regm are 4bit variables
|
||||
if fptrace > 0 {
|
||||
print("*** fix unsigned S[", regd, "]=D[", regm, "] ", hex(m.freglo[regd]), "\n")
|
||||
}
|
||||
break
|
||||
return 1
|
||||
|
||||
case 0xeeb80ac0: // D[regd] = S[regm] (MOVWF)
|
||||
cmp = int32(m.freglo[regm])
|
||||
cmp := int32(m.freglo[regm])
|
||||
if cmp < 0 {
|
||||
fintto64c(int64(-cmp), &uval)
|
||||
fputf(regd, f64to32(uval))
|
||||
fputf(regd, f64to32(fintto64(int64(-cmp))))
|
||||
m.freglo[regd] ^= 0x80000000
|
||||
} else {
|
||||
fintto64c(int64(cmp), &uval)
|
||||
fputf(regd, f64to32(uval))
|
||||
fputf(regd, f64to32(fintto64(int64(cmp))))
|
||||
}
|
||||
|
||||
if fptrace > 0 {
|
||||
print("*** float D[", regd, "]=S[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
|
||||
}
|
||||
break
|
||||
return 1
|
||||
|
||||
case 0xeeb80a40: // D[regd] = S[regm] (MOVWF.U)
|
||||
fintto64c(int64(m.freglo[regm]), &uval)
|
||||
fputf(regd, f64to32(uval))
|
||||
fputf(regd, f64to32(fintto64(int64(m.freglo[regm]))))
|
||||
|
||||
if fptrace > 0 {
|
||||
print("*** float unsigned D[", regd, "]=S[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
|
||||
}
|
||||
break
|
||||
return 1
|
||||
|
||||
case 0xeeb80bc0: // D[regd] = S[regm] (MOVWD)
|
||||
cmp = int32(m.freglo[regm])
|
||||
cmp := int32(m.freglo[regm])
|
||||
if cmp < 0 {
|
||||
fintto64c(int64(-cmp), &uval)
|
||||
fputd(regd, uval)
|
||||
fputd(regd, fintto64(int64(-cmp)))
|
||||
m.freghi[regd] ^= 0x80000000
|
||||
} else {
|
||||
fintto64c(int64(cmp), &uval)
|
||||
fputd(regd, uval)
|
||||
fputd(regd, fintto64(int64(cmp)))
|
||||
}
|
||||
|
||||
if fptrace > 0 {
|
||||
print("*** float D[", regd, "]=S[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
|
||||
}
|
||||
break
|
||||
return 1
|
||||
|
||||
case 0xeeb80b40: // D[regd] = S[regm] (MOVWD.U)
|
||||
fintto64c(int64(m.freglo[regm]), &uval)
|
||||
fputd(regd, uval)
|
||||
fputd(regd, fintto64(int64(m.freglo[regm])))
|
||||
|
||||
if fptrace > 0 {
|
||||
print("*** float unsigned D[", regd, "]=S[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
|
||||
}
|
||||
break
|
||||
return 1
|
||||
}
|
||||
return 1
|
||||
|
||||
done:
|
||||
if i&0xff000000 == 0xee000000 ||
|
||||
i&0xff000000 == 0xed000000 {
|
||||
if i&0xff000000 == 0xee000000 || i&0xff000000 == 0xed000000 {
|
||||
print("stepflt ", pc, " ", hex(i), "\n")
|
||||
fabort()
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user