From 2101b9fd446f28f856986b27d20f92cd4a1f4fef Mon Sep 17 00:00:00 2001
From: Mauri de Souza Meneguzzo <mauri870@gmail.com>
Date: Tue, 17 Oct 2023 19:43:21 -0300
Subject: [PATCH] runtime/internal/atomic: add memory barrier for mips Cas on
 failure

Add a memory barrier on the failure case of the
compare-and-swap for mips, this avoids potential
race conditions.

For #63506
---
 src/runtime/internal/atomic/atomic_mipsx.go | 7 +------
 src/runtime/internal/atomic/atomic_mipsx.s  | 1 +
 2 files changed, 2 insertions(+), 6 deletions(-)

diff --git a/src/runtime/internal/atomic/atomic_mipsx.go b/src/runtime/internal/atomic/atomic_mipsx.go
index 5dd15a0b022..e3dcde1bde9 100644
--- a/src/runtime/internal/atomic/atomic_mipsx.go
+++ b/src/runtime/internal/atomic/atomic_mipsx.go
@@ -48,11 +48,6 @@ func unlock() {
 	spinUnlock(&lock.state)
 }
 
-//go:nosplit
-func unlockNoFence() {
-	lock.state = 0
-}
-
 //go:nosplit
 func Xadd64(addr *uint64, delta int64) (new uint64) {
 	lockAndCheck(addr)
@@ -85,7 +80,7 @@ func Cas64(addr *uint64, old, new uint64) (swapped bool) {
 		return true
 	}
 
-	unlockNoFence()
+	unlock()
 	return false
 }
 
diff --git a/src/runtime/internal/atomic/atomic_mipsx.s b/src/runtime/internal/atomic/atomic_mipsx.s
index 390e9ce7acc..8f5fc53cb77 100644
--- a/src/runtime/internal/atomic/atomic_mipsx.s
+++ b/src/runtime/internal/atomic/atomic_mipsx.s
@@ -28,6 +28,7 @@ try_cas:
 	MOVB	R3, ret+12(FP)
 	RET
 cas_fail:
+	SYNC
 	MOVB	R0, ret+12(FP)
 	RET