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[dev.ssa] cmd/compile: lots of small rewrite optimizations
Small optimizations I noticed while looking at Giovanni's test cases. More shifts by constants. Indexed stores for smaller types. Fold LEA into loads/stores. More extending loads. CMP $0 of AND -> TEST Fix order of TEST ops. Giovanni's test cases at https://gist.github.com/rasky/62fba94e3a20d1b05b2a Change-Id: I7077bc0b5319bf05767eeb39f401f4bb4b39f635 Reviewed-on: https://go-review.googlesource.com/19086 Run-TryBot: Keith Randall <khr@golang.org> Reviewed-by: Todd Neal <todd@tneal.org> Reviewed-by: David Chase <drchase@google.com>
This commit is contained in:
Keith Randall
parent
f962f33035
commit
1cc5789df9
@ -4003,13 +4003,18 @@ func (s *genState) genValue(v *ssa.Value) {
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// Go assembler has swapped operands for UCOMISx relative to CMP,
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// must account for that right here.
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opregreg(v.Op.Asm(), regnum(v.Args[0]), regnum(v.Args[1]))
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case ssa.OpAMD64CMPQconst, ssa.OpAMD64CMPLconst, ssa.OpAMD64CMPWconst, ssa.OpAMD64CMPBconst,
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ssa.OpAMD64TESTQconst, ssa.OpAMD64TESTLconst, ssa.OpAMD64TESTWconst, ssa.OpAMD64TESTBconst:
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case ssa.OpAMD64CMPQconst, ssa.OpAMD64CMPLconst, ssa.OpAMD64CMPWconst, ssa.OpAMD64CMPBconst:
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p := Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = regnum(v.Args[0])
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p.To.Type = obj.TYPE_CONST
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p.To.Offset = v.AuxInt
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case ssa.OpAMD64TESTQconst, ssa.OpAMD64TESTLconst, ssa.OpAMD64TESTWconst, ssa.OpAMD64TESTBconst:
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p := Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_CONST
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p.From.Offset = v.AuxInt
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p.To.Type = obj.TYPE_REG
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p.To.Reg = regnum(v.Args[0])
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case ssa.OpAMD64MOVBconst, ssa.OpAMD64MOVWconst, ssa.OpAMD64MOVLconst, ssa.OpAMD64MOVQconst:
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x := regnum(v)
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p := Prog(v.Op.Asm())
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@ -4040,7 +4045,7 @@ func (s *genState) genValue(v *ssa.Value) {
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p.From.Val = math.Float64frombits(uint64(v.AuxInt))
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p.To.Type = obj.TYPE_REG
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p.To.Reg = x
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case ssa.OpAMD64MOVQload, ssa.OpAMD64MOVSSload, ssa.OpAMD64MOVSDload, ssa.OpAMD64MOVLload, ssa.OpAMD64MOVWload, ssa.OpAMD64MOVBload, ssa.OpAMD64MOVBQSXload, ssa.OpAMD64MOVBQZXload, ssa.OpAMD64MOVOload:
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case ssa.OpAMD64MOVQload, ssa.OpAMD64MOVSSload, ssa.OpAMD64MOVSDload, ssa.OpAMD64MOVLload, ssa.OpAMD64MOVWload, ssa.OpAMD64MOVBload, ssa.OpAMD64MOVBQSXload, ssa.OpAMD64MOVBQZXload, ssa.OpAMD64MOVWQSXload, ssa.OpAMD64MOVWQZXload, ssa.OpAMD64MOVLQSXload, ssa.OpAMD64MOVLQZXload, ssa.OpAMD64MOVOload:
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p := Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_MEM
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p.From.Reg = regnum(v.Args[0])
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@ -4081,7 +4086,7 @@ func (s *genState) genValue(v *ssa.Value) {
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p.To.Scale = 8
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p.To.Index = regnum(v.Args[1])
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addAux(&p.To, v)
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case ssa.OpAMD64MOVSSstoreidx4:
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case ssa.OpAMD64MOVSSstoreidx4, ssa.OpAMD64MOVLstoreidx4:
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p := Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = regnum(v.Args[2])
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@ -4090,6 +4095,24 @@ func (s *genState) genValue(v *ssa.Value) {
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p.To.Scale = 4
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p.To.Index = regnum(v.Args[1])
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addAux(&p.To, v)
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case ssa.OpAMD64MOVWstoreidx2:
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p := Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = regnum(v.Args[2])
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p.To.Type = obj.TYPE_MEM
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p.To.Reg = regnum(v.Args[0])
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p.To.Scale = 2
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p.To.Index = regnum(v.Args[1])
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addAux(&p.To, v)
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case ssa.OpAMD64MOVBstoreidx1:
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p := Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = regnum(v.Args[2])
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p.To.Type = obj.TYPE_MEM
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p.To.Reg = regnum(v.Args[0])
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p.To.Scale = 1
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p.To.Index = regnum(v.Args[1])
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addAux(&p.To, v)
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case ssa.OpAMD64MOVQstoreconst, ssa.OpAMD64MOVLstoreconst, ssa.OpAMD64MOVWstoreconst, ssa.OpAMD64MOVBstoreconst:
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p := Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_CONST
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@ -4365,7 +4388,9 @@ func (s *genState) genValue(v *ssa.Value) {
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}
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switch w.Op {
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case ssa.OpAMD64MOVQload, ssa.OpAMD64MOVLload, ssa.OpAMD64MOVWload, ssa.OpAMD64MOVBload,
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ssa.OpAMD64MOVQstore, ssa.OpAMD64MOVLstore, ssa.OpAMD64MOVWstore, ssa.OpAMD64MOVBstore:
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ssa.OpAMD64MOVQstore, ssa.OpAMD64MOVLstore, ssa.OpAMD64MOVWstore, ssa.OpAMD64MOVBstore,
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ssa.OpAMD64MOVBQSXload, ssa.OpAMD64MOVBQZXload, ssa.OpAMD64MOVWQSXload,
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ssa.OpAMD64MOVWQZXload, ssa.OpAMD64MOVLQSXload, ssa.OpAMD64MOVLQZXload:
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if w.Args[0] == v.Args[0] && w.Aux == nil && w.AuxInt >= 0 && w.AuxInt < minZeroPage {
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if Debug_checknil != 0 && int(v.Line) > 1 {
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Warnl(int(v.Line), "removed nil check")
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@ -51,6 +51,8 @@ Optimizations (better compiled code)
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Note that this is challenging for ops that generate flags
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because flagalloc wants to move those instructions around for
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flag regeneration.
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- In forms like if ... { call } else { no call }, mark the call branch as unlikely.
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- Non-constant rotate detection.
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Optimizations (better compiler)
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-------------------------------
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@ -464,18 +464,63 @@
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(XORB (MOVBconst [c]) x) -> (XORBconst [c] x)
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(SHLQ x (MOVQconst [c])) -> (SHLQconst [c&63] x)
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(SHLQ x (MOVLconst [c])) -> (SHLQconst [c&63] x)
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(SHLQ x (MOVWconst [c])) -> (SHLQconst [c&63] x)
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(SHLQ x (MOVBconst [c])) -> (SHLQconst [c&63] x)
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(SHLL x (MOVQconst [c])) -> (SHLLconst [c&31] x)
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(SHLL x (MOVLconst [c])) -> (SHLLconst [c&31] x)
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(SHLL x (MOVWconst [c])) -> (SHLLconst [c&31] x)
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(SHLL x (MOVBconst [c])) -> (SHLLconst [c&31] x)
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(SHLW x (MOVQconst [c])) -> (SHLWconst [c&31] x)
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(SHLW x (MOVLconst [c])) -> (SHLWconst [c&31] x)
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(SHLW x (MOVWconst [c])) -> (SHLWconst [c&31] x)
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(SHLW x (MOVBconst [c])) -> (SHLWconst [c&31] x)
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(SHLB x (MOVQconst [c])) -> (SHLBconst [c&31] x)
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(SHLB x (MOVLconst [c])) -> (SHLBconst [c&31] x)
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(SHLB x (MOVWconst [c])) -> (SHLBconst [c&31] x)
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(SHLB x (MOVBconst [c])) -> (SHLBconst [c&31] x)
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(SHRQ x (MOVQconst [c])) -> (SHRQconst [c&63] x)
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(SHRQ x (MOVLconst [c])) -> (SHRQconst [c&63] x)
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(SHRQ x (MOVWconst [c])) -> (SHRQconst [c&63] x)
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(SHRQ x (MOVBconst [c])) -> (SHRQconst [c&63] x)
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(SHRL x (MOVQconst [c])) -> (SHRLconst [c&31] x)
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(SHRL x (MOVLconst [c])) -> (SHRLconst [c&31] x)
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(SHRL x (MOVWconst [c])) -> (SHRLconst [c&31] x)
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(SHRL x (MOVBconst [c])) -> (SHRLconst [c&31] x)
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(SHRW x (MOVQconst [c])) -> (SHRWconst [c&31] x)
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(SHRW x (MOVLconst [c])) -> (SHRWconst [c&31] x)
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(SHRW x (MOVWconst [c])) -> (SHRWconst [c&31] x)
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(SHRW x (MOVBconst [c])) -> (SHRWconst [c&31] x)
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(SHRB x (MOVQconst [c])) -> (SHRBconst [c&31] x)
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(SHRB x (MOVLconst [c])) -> (SHRBconst [c&31] x)
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(SHRB x (MOVWconst [c])) -> (SHRBconst [c&31] x)
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(SHRB x (MOVBconst [c])) -> (SHRBconst [c&31] x)
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(SARQ x (MOVQconst [c])) -> (SARQconst [c&63] x)
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(SARQ x (MOVLconst [c])) -> (SARQconst [c&63] x)
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(SARQ x (MOVWconst [c])) -> (SARQconst [c&63] x)
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(SARQ x (MOVBconst [c])) -> (SARQconst [c&63] x)
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(SARL x (MOVQconst [c])) -> (SARLconst [c&31] x)
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(SARL x (MOVLconst [c])) -> (SARLconst [c&31] x)
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(SARL x (MOVWconst [c])) -> (SARLconst [c&31] x)
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(SARL x (MOVBconst [c])) -> (SARLconst [c&31] x)
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(SARW x (MOVQconst [c])) -> (SARWconst [c&31] x)
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(SARW x (MOVLconst [c])) -> (SARWconst [c&31] x)
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(SARW x (MOVWconst [c])) -> (SARWconst [c&31] x)
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(SARW x (MOVBconst [c])) -> (SARWconst [c&31] x)
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(SARB x (MOVQconst [c])) -> (SARBconst [c&31] x)
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(SARB x (MOVLconst [c])) -> (SARBconst [c&31] x)
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(SARB x (MOVWconst [c])) -> (SARBconst [c&31] x)
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(SARB x (MOVBconst [c])) -> (SARBconst [c&31] x)
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// Note: the word and byte shifts keep the low 5 bits (not the low 4 or 3 bits)
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@ -524,7 +569,18 @@
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// multiple memory values alive simultaneously.
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(MOVBQSX (MOVBload [off] {sym} ptr mem)) -> @v.Args[0].Block (MOVBQSXload <v.Type> [off] {sym} ptr mem)
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(MOVBQZX (MOVBload [off] {sym} ptr mem)) -> @v.Args[0].Block (MOVBQZXload <v.Type> [off] {sym} ptr mem)
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// TODO: more
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(MOVWQSX (MOVWload [off] {sym} ptr mem)) -> @v.Args[0].Block (MOVWQSXload <v.Type> [off] {sym} ptr mem)
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(MOVWQZX (MOVWload [off] {sym} ptr mem)) -> @v.Args[0].Block (MOVWQZXload <v.Type> [off] {sym} ptr mem)
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(MOVLQSX (MOVLload [off] {sym} ptr mem)) -> @v.Args[0].Block (MOVLQSXload <v.Type> [off] {sym} ptr mem)
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(MOVLQZX (MOVLload [off] {sym} ptr mem)) -> @v.Args[0].Block (MOVLQZXload <v.Type> [off] {sym} ptr mem)
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// Fold extensions and ANDs together.
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(MOVBQZX (ANDBconst [c] x)) -> (ANDQconst [c & 0xff] x)
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(MOVWQZX (ANDWconst [c] x)) -> (ANDQconst [c & 0xffff] x)
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(MOVLQZX (ANDLconst [c] x)) -> (ANDQconst [c & 0xffffffff] x)
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(MOVBQSX (ANDBconst [c] x)) && c & 0x80 == 0 -> (ANDQconst [c & 0x7f] x)
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(MOVWQSX (ANDWconst [c] x)) && c & 0x8000 == 0 -> (ANDQconst [c & 0x7fff] x)
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(MOVLQSX (ANDLconst [c] x)) && c & 0x80000000 == 0 -> (ANDQconst [c & 0x7fffffff] x)
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// Don't extend before storing
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(MOVLstore [off] {sym} ptr (MOVLQSX x) mem) -> (MOVLstore [off] {sym} ptr x mem)
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@ -623,22 +679,63 @@
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(MOVSSstoreidx4 [off1] {sym} (ADDQconst [off2] {sym} ptr) idx val mem) -> (MOVSSstoreidx4 [addOff(off1, off2)] {sym} ptr idx val mem)
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(MOVSDloadidx8 [off1] {sym} (ADDQconst [off2] {sym} ptr) idx mem) -> (MOVSDloadidx8 [addOff(off1, off2)] {sym} ptr idx mem)
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(MOVSDstoreidx8 [off1] {sym} (ADDQconst [off2] {sym} ptr) idx val mem) -> (MOVSDstoreidx8 [addOff(off1, off2)] {sym} ptr idx val mem)
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(MOVLstoreidx4 [off1] {sym} (ADDQconst [off2] ptr) idx val mem) -> (MOVLstoreidx4 [addOff(off1, off2)] {sym} ptr idx val mem)
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(MOVWstoreidx2 [off1] {sym} (ADDQconst [off2] ptr) idx val mem) -> (MOVWstoreidx2 [addOff(off1, off2)] {sym} ptr idx val mem)
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(MOVBstoreidx1 [off1] {sym} (ADDQconst [off2] ptr) idx val mem) -> (MOVBstoreidx1 [addOff(off1, off2)] {sym} ptr idx val mem)
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(MOVQload [off1] {sym1} (LEAQ8 [off2] {sym2} ptr idx) mem) && canMergeSym(sym1, sym2) ->
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(MOVQloadidx8 [addOff(off1, off2)] {mergeSym(sym1,sym2)} ptr idx mem)
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(MOVQstore [off1] {sym1} (LEAQ8 [off2] {sym2} ptr idx) val mem) && canMergeSym(sym1, sym2) ->
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(MOVQstoreidx8 [addOff(off1, off2)] {mergeSym(sym1,sym2)} ptr idx val mem)
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(MOVSSload [off1] {sym1} (LEAQ4 [off2] {sym2} ptr idx) mem) && canMergeSym(sym1, sym2) ->
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(MOVSSloadidx4 [addOff(off1, off2)] {mergeSym(sym1,sym2)} ptr idx mem)
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(MOVSSstore [off1] {sym1} (LEAQ4 [off2] {sym2} ptr idx) val mem) && canMergeSym(sym1, sym2) ->
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(MOVSSstoreidx4 [addOff(off1, off2)] {mergeSym(sym1,sym2)} ptr idx val mem)
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(MOVSDload [off1] {sym1} (LEAQ8 [off2] {sym2} ptr idx) mem) && canMergeSym(sym1, sym2) ->
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(MOVSDloadidx8 [addOff(off1, off2)] {mergeSym(sym1,sym2)} ptr idx mem)
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(MOVBstore [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) val mem) && canMergeSym(sym1, sym2) ->
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(MOVBstoreidx1 [addOff(off1, off2)] {mergeSym(sym1,sym2)} ptr idx val mem)
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(MOVWstore [off1] {sym1} (LEAQ2 [off2] {sym2} ptr idx) val mem) && canMergeSym(sym1, sym2) ->
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(MOVWstoreidx2 [addOff(off1, off2)] {mergeSym(sym1,sym2)} ptr idx val mem)
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(MOVLstore [off1] {sym1} (LEAQ4 [off2] {sym2} ptr idx) val mem) && canMergeSym(sym1, sym2) ->
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(MOVLstoreidx4 [addOff(off1, off2)] {mergeSym(sym1,sym2)} ptr idx val mem)
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(MOVQstore [off1] {sym1} (LEAQ8 [off2] {sym2} ptr idx) val mem) && canMergeSym(sym1, sym2) ->
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(MOVQstoreidx8 [addOff(off1, off2)] {mergeSym(sym1,sym2)} ptr idx val mem)
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(MOVSSstore [off1] {sym1} (LEAQ4 [off2] {sym2} ptr idx) val mem) && canMergeSym(sym1, sym2) ->
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(MOVSSstoreidx4 [addOff(off1, off2)] {mergeSym(sym1,sym2)} ptr idx val mem)
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(MOVSDstore [off1] {sym1} (LEAQ8 [off2] {sym2} ptr idx) val mem) && canMergeSym(sym1, sym2) ->
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(MOVSDstoreidx8 [addOff(off1, off2)] {mergeSym(sym1,sym2)} ptr idx val mem)
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(MOVBstore [off] {sym} (ADDQ ptr idx) val mem) -> (MOVBstoreidx1 [off] {sym} ptr idx val mem)
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// fold LEAQs together
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(LEAQ [off1] {sym1} (LEAQ [off2] {sym2} x)) && canMergeSym(sym1, sym2) ->
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(LEAQ [addOff(off1,off2)] {mergeSym(sym1,sym2)} x)
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// LEAQ into LEAQ1
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(LEAQ1 [off1] {sym1} (LEAQ [off2] {sym2} x) y) && canMergeSym(sym1, sym2) && x.Op != OpSB ->
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(LEAQ1 [addOff(off1,off2)] {mergeSym(sym1,sym2)} x y)
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(LEAQ1 [off1] {sym1} x (LEAQ [off2] {sym2} y)) && canMergeSym(sym1, sym2) && y.Op != OpSB ->
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(LEAQ1 [addOff(off1,off2)] {mergeSym(sym1,sym2)} x y)
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// LEAQ1 into LEAQ
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(LEAQ [off1] {sym1} (LEAQ1 [off2] {sym2} x y)) && canMergeSym(sym1, sym2) ->
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(LEAQ1 [addOff(off1,off2)] {mergeSym(sym1,sym2)} x y)
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// LEAQ into LEAQ[248]
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(LEAQ2 [off1] {sym1} (LEAQ [off2] {sym2} x) y) && canMergeSym(sym1, sym2) && x.Op != OpSB ->
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(LEAQ2 [addOff(off1,off2)] {mergeSym(sym1,sym2)} x y)
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(LEAQ4 [off1] {sym1} (LEAQ [off2] {sym2} x) y) && canMergeSym(sym1, sym2) && x.Op != OpSB ->
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(LEAQ4 [addOff(off1,off2)] {mergeSym(sym1,sym2)} x y)
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(LEAQ8 [off1] {sym1} (LEAQ [off2] {sym2} x) y) && canMergeSym(sym1, sym2) && x.Op != OpSB ->
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(LEAQ8 [addOff(off1,off2)] {mergeSym(sym1,sym2)} x y)
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// LEAQ[248] into LEAQ
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(LEAQ [off1] {sym1} (LEAQ2 [off2] {sym2} x y)) && canMergeSym(sym1, sym2) ->
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(LEAQ2 [addOff(off1,off2)] {mergeSym(sym1,sym2)} x y)
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(LEAQ [off1] {sym1} (LEAQ4 [off2] {sym2} x y)) && canMergeSym(sym1, sym2) ->
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(LEAQ4 [addOff(off1,off2)] {mergeSym(sym1,sym2)} x y)
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(LEAQ [off1] {sym1} (LEAQ8 [off2] {sym2} x y)) && canMergeSym(sym1, sym2) ->
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(LEAQ8 [addOff(off1,off2)] {mergeSym(sym1,sym2)} x y)
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// lower Zero instructions with word sizes
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(Zero [0] _ mem) -> mem
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(Zero [1] destptr mem) -> (MOVBstoreconst [0] destptr mem)
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@ -963,3 +1060,12 @@
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(XORW x x) -> (MOVWconst [0])
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(XORB x x) -> (MOVBconst [0])
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// checking AND against 0.
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(CMPQconst (ANDQ x y) [0]) -> (TESTQ x y)
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(CMPLconst (ANDL x y) [0]) -> (TESTL x y)
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(CMPWconst (ANDW x y) [0]) -> (TESTW x y)
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(CMPBconst (ANDB x y) [0]) -> (TESTB x y)
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(CMPQconst (ANDQconst [c] x) [0]) -> (TESTQconst [c] x)
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(CMPLconst (ANDLconst [c] x) [0]) -> (TESTLconst [c] x)
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(CMPWconst (ANDWconst [c] x) [0]) -> (TESTWconst [c] x)
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(CMPBconst (ANDBconst [c] x) [0]) -> (TESTBconst [c] x)
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@ -368,14 +368,22 @@ func init() {
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{name: "MOVBQSXload", reg: gpload, asm: "MOVBQSX"}, // ditto, extend to int64
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{name: "MOVBQZXload", reg: gpload, asm: "MOVBQZX"}, // ditto, extend to uint64
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{name: "MOVWload", reg: gpload, asm: "MOVW", typ: "UInt16"}, // load 2 bytes from arg0+auxint+aux. arg1=mem
|
||||
{name: "MOVWQSXload", reg: gpload, asm: "MOVWQSX"}, // ditto, extend to int64
|
||||
{name: "MOVWQZXload", reg: gpload, asm: "MOVWQZX"}, // ditto, extend to uint64
|
||||
{name: "MOVLload", reg: gpload, asm: "MOVL", typ: "UInt32"}, // load 4 bytes from arg0+auxint+aux. arg1=mem
|
||||
{name: "MOVLQSXload", reg: gpload, asm: "MOVLQSX"}, // ditto, extend to int64
|
||||
{name: "MOVLQZXload", reg: gpload, asm: "MOVLQZX"}, // ditto, extend to uint64
|
||||
{name: "MOVQload", reg: gpload, asm: "MOVQ", typ: "UInt64"}, // load 8 bytes from arg0+auxint+aux. arg1=mem
|
||||
{name: "MOVQloadidx8", reg: gploadidx, asm: "MOVQ"}, // load 8 bytes from arg0+8*arg1+auxint+aux. arg2=mem
|
||||
{name: "MOVBstore", reg: gpstore, asm: "MOVB", typ: "Mem"}, // store byte in arg1 to arg0+auxint+aux. arg2=mem
|
||||
{name: "MOVWstore", reg: gpstore, asm: "MOVW", typ: "Mem"}, // store 2 bytes in arg1 to arg0+auxint+aux. arg2=mem
|
||||
{name: "MOVLstore", reg: gpstore, asm: "MOVL", typ: "Mem"}, // store 4 bytes in arg1 to arg0+auxint+aux. arg2=mem
|
||||
{name: "MOVQstore", reg: gpstore, asm: "MOVQ", typ: "Mem"}, // store 8 bytes in arg1 to arg0+auxint+aux. arg2=mem
|
||||
{name: "MOVQstoreidx8", reg: gpstoreidx, asm: "MOVQ"}, // store 8 bytes in arg2 to arg0+8*arg1+auxint+aux. arg3=mem
|
||||
|
||||
{name: "MOVBstoreidx1", reg: gpstoreidx, asm: "MOVB"}, // store byte in arg2 to arg0+arg1+auxint+aux. arg3=mem
|
||||
{name: "MOVWstoreidx2", reg: gpstoreidx, asm: "MOVW"}, // store 2 bytes in arg2 to arg0+2*arg1+auxint+aux. arg3=mem
|
||||
{name: "MOVLstoreidx4", reg: gpstoreidx, asm: "MOVL"}, // store 4 bytes in arg2 to arg0+4*arg1+auxint+aux. arg3=mem
|
||||
{name: "MOVQstoreidx8", reg: gpstoreidx, asm: "MOVQ"}, // store 8 bytes in arg2 to arg0+8*arg1+auxint+aux. arg3=mem
|
||||
|
||||
{name: "MOVOload", reg: fpload, asm: "MOVUPS", typ: "Int128"}, // load 16 bytes from arg0+auxint+aux. arg1=mem
|
||||
{name: "MOVOstore", reg: fpstore, asm: "MOVUPS", typ: "Mem"}, // store 16 bytes in arg1 to arg0+auxint+aux. arg2=mem
|
||||
|
||||
@ -254,13 +254,20 @@ const (
|
||||
OpAMD64MOVBQSXload
|
||||
OpAMD64MOVBQZXload
|
||||
OpAMD64MOVWload
|
||||
OpAMD64MOVWQSXload
|
||||
OpAMD64MOVWQZXload
|
||||
OpAMD64MOVLload
|
||||
OpAMD64MOVLQSXload
|
||||
OpAMD64MOVLQZXload
|
||||
OpAMD64MOVQload
|
||||
OpAMD64MOVQloadidx8
|
||||
OpAMD64MOVBstore
|
||||
OpAMD64MOVWstore
|
||||
OpAMD64MOVLstore
|
||||
OpAMD64MOVQstore
|
||||
OpAMD64MOVBstoreidx1
|
||||
OpAMD64MOVWstoreidx2
|
||||
OpAMD64MOVLstoreidx4
|
||||
OpAMD64MOVQstoreidx8
|
||||
OpAMD64MOVOload
|
||||
OpAMD64MOVOstore
|
||||
@ -2966,6 +2973,30 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "MOVWQSXload",
|
||||
asm: x86.AMOVWQSX,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
||||
},
|
||||
outputs: []regMask{
|
||||
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "MOVWQZXload",
|
||||
asm: x86.AMOVWQZX,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
||||
},
|
||||
outputs: []regMask{
|
||||
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "MOVLload",
|
||||
asm: x86.AMOVL,
|
||||
@ -2978,6 +3009,30 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "MOVLQSXload",
|
||||
asm: x86.AMOVLQSX,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
||||
},
|
||||
outputs: []regMask{
|
||||
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "MOVLQZXload",
|
||||
asm: x86.AMOVLQZX,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
||||
},
|
||||
outputs: []regMask{
|
||||
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "MOVQload",
|
||||
asm: x86.AMOVQ,
|
||||
@ -3043,6 +3098,39 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "MOVBstoreidx1",
|
||||
asm: x86.AMOVB,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
||||
{2, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
||||
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "MOVWstoreidx2",
|
||||
asm: x86.AMOVW,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
||||
{2, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
||||
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "MOVLstoreidx4",
|
||||
asm: x86.AMOVL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
||||
{2, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
||||
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "MOVQstoreidx8",
|
||||
asm: x86.AMOVQ,
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user