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cmd/compile: lowered MulUintptr on riscv64
According to RISCV instruction set manual v2.2 Sec 6.1 MULHU followed by MUL will be fused into one multiply by microarchitecture name old time/op new time/op delta MulUintptr/small 11.2ns ±24% 9.2ns ± 0% -17.54% (p=0.000 n=10+9) MulUintptr/large 15.9ns ± 0% 10.9ns ± 0% -31.55% (p=0.000 n=8+8) Change-Id: I3d152218f83948cbc5c576bda29dc86e9b4206ee Reviewed-on: https://go-review.googlesource.com/c/go/+/338753 Trust: Meng Zhuo <mzh@golangcn.org> Reviewed-by: Joel Sing <joel@sing.id.au>
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@ -297,6 +297,27 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
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p1.Reg = r0
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p1.To.Type = obj.TYPE_REG
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p1.To.Reg = v.Reg1()
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case ssa.OpRISCV64LoweredMuluover:
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r0 := v.Args[0].Reg()
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r1 := v.Args[1].Reg()
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p := s.Prog(riscv.AMULHU)
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p.From.Type = obj.TYPE_REG
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p.From.Reg = r1
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p.Reg = r0
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p.To.Type = obj.TYPE_REG
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p.To.Reg = v.Reg1()
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p1 := s.Prog(riscv.AMUL)
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p1.From.Type = obj.TYPE_REG
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p1.From.Reg = r1
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p1.Reg = r0
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p1.To.Type = obj.TYPE_REG
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p1.To.Reg = v.Reg0()
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p2 := s.Prog(riscv.ASNEZ)
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p2.From.Type = obj.TYPE_REG
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p2.From.Reg = v.Reg1()
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p2.To.Type = obj.TYPE_REG
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p2.To.Reg = v.Reg1()
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case ssa.OpRISCV64FSQRTS, ssa.OpRISCV64FNEGS, ssa.OpRISCV64FSQRTD, ssa.OpRISCV64FNEGD,
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ssa.OpRISCV64FMVSX, ssa.OpRISCV64FMVDX,
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ssa.OpRISCV64FCVTSW, ssa.OpRISCV64FCVTSL, ssa.OpRISCV64FCVTWS, ssa.OpRISCV64FCVTLS,
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@ -30,6 +30,7 @@
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(Mul64 ...) => (MUL ...)
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(Mul64uhilo ...) => (LoweredMuluhilo ...)
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(Mul64uover ...) => (LoweredMuluover ...)
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(Mul32 ...) => (MULW ...)
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(Mul16 x y) => (MULW (SignExt16to32 x) (SignExt16to32 y))
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(Mul8 x y) => (MULW (SignExt8to32 x) (SignExt8to32 y))
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@ -159,6 +159,7 @@ func init() {
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{name: "MULH", argLength: 2, reg: gp21, asm: "MULH", commutative: true, typ: "Int64"},
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{name: "MULHU", argLength: 2, reg: gp21, asm: "MULHU", commutative: true, typ: "UInt64"},
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{name: "LoweredMuluhilo", argLength: 2, reg: gp22, resultNotInArgs: true}, // arg0 * arg1, return (hi, lo)
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{name: "LoweredMuluover", argLength: 2, reg: gp22, resultNotInArgs: true}, // arg0 * arg1, return (64 bits of arg0*arg1, overflow)
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{name: "DIV", argLength: 2, reg: gp21, asm: "DIV", typ: "Int64"}, // arg0 / arg1
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{name: "DIVU", argLength: 2, reg: gp21, asm: "DIVU", typ: "UInt64"},
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@ -2070,6 +2070,7 @@ const (
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OpRISCV64MULH
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OpRISCV64MULHU
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OpRISCV64LoweredMuluhilo
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OpRISCV64LoweredMuluover
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OpRISCV64DIV
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OpRISCV64DIVU
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OpRISCV64DIVW
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@ -27619,6 +27620,21 @@ var opcodeTable = [...]opInfo{
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},
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},
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},
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{
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name: "LoweredMuluover",
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argLen: 2,
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resultNotInArgs: true,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 1006632948}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
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{1, 1006632948}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
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},
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outputs: []outputInfo{
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{0, 1006632948}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
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{1, 1006632948}, // X3 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
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},
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},
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},
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{
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name: "DIV",
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argLen: 2,
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@ -359,6 +359,9 @@ func rewriteValueRISCV64(v *Value) bool {
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case OpMul64uhilo:
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v.Op = OpRISCV64LoweredMuluhilo
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return true
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case OpMul64uover:
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v.Op = OpRISCV64LoweredMuluover
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return true
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case OpMul8:
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return rewriteValueRISCV64_OpMul8(v)
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case OpNeg16:
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@ -3779,7 +3779,7 @@ func InitTables() {
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}
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return s.newValue2(ssa.OpMul64uover, types.NewTuple(types.Types[types.TUINT], types.Types[types.TUINT]), args[0], args[1])
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},
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sys.AMD64, sys.I386, sys.MIPS64)
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sys.AMD64, sys.I386, sys.MIPS64, sys.RISCV64)
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add("runtime", "KeepAlive",
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func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
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data := s.newValue1(ssa.OpIData, s.f.Config.Types.BytePtr, args[0])
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