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cmd/compile/internal/ssa: remove Hmul{8,16}{,u} ops
Change-Id: I90865921584ae4bdfb6c220d439b14593d72b6f9 Reviewed-on: https://go-review.googlesource.com/37752 Run-TryBot: Matthew Dempsky <mdempsky@google.com> TryBot-Result: Gobot Gobot <gobot@golang.org> Reviewed-by: Cherry Zhang <cherryyz@google.com>
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@ -281,8 +281,7 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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j1.To.Val = n1
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j2.To.Val = s.Pc()
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case ssa.OpAMD64HMULQ, ssa.OpAMD64HMULL, ssa.OpAMD64HMULW, ssa.OpAMD64HMULB,
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ssa.OpAMD64HMULQU, ssa.OpAMD64HMULLU, ssa.OpAMD64HMULWU, ssa.OpAMD64HMULBU:
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case ssa.OpAMD64HMULQ, ssa.OpAMD64HMULL, ssa.OpAMD64HMULQU, ssa.OpAMD64HMULLU:
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// the frontend rewrites constant division by 8/16/32 bit integers into
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// HMUL by a constant
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// SSA rewrites generate the 64 bit versions
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@ -45,10 +45,6 @@
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(Hmul32 x y) -> (HMULL x y)
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(Hmul32u x y) -> (HMULLU x y)
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(Hmul16 x y) -> (HMULW x y)
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(Hmul16u x y) -> (HMULWU x y)
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(Hmul8 x y) -> (HMULB x y)
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(Hmul8u x y) -> (HMULBU x y)
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(Mod32 x y) -> (MODL x y)
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(Mod32u x y) -> (MODLU x y)
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@ -195,10 +195,6 @@ func init() {
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{name: "HMULL", argLength: 2, reg: gp21hmul, asm: "IMULL", clobberFlags: true}, // (arg0 * arg1) >> width
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{name: "HMULLU", argLength: 2, reg: gp21hmul, asm: "MULL", clobberFlags: true}, // (arg0 * arg1) >> width
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{name: "HMULW", argLength: 2, reg: gp21hmul, asm: "IMULW", clobberFlags: true}, // (arg0 * arg1) >> width
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{name: "HMULB", argLength: 2, reg: gp21hmul, asm: "IMULB", clobberFlags: true}, // (arg0 * arg1) >> width
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{name: "HMULWU", argLength: 2, reg: gp21hmul, asm: "MULW", clobberFlags: true}, // (arg0 * arg1) >> width
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{name: "HMULBU", argLength: 2, reg: gp21hmul, asm: "MULB", clobberFlags: true}, // (arg0 * arg1) >> width
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{name: "MULLQU", argLength: 2, reg: gp21mul, asm: "MULL", clobberFlags: true}, // arg0 * arg1, high 32 in result[0], low 32 in result[1]
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@ -44,10 +44,6 @@
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(Hmul64u x y) -> (HMULQU x y)
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(Hmul32 x y) -> (HMULL x y)
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(Hmul32u x y) -> (HMULLU x y)
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(Hmul16 x y) -> (HMULW x y)
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(Hmul16u x y) -> (HMULWU x y)
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(Hmul8 x y) -> (HMULB x y)
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(Hmul8u x y) -> (HMULBU x y)
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(Mul64uhilo x y) -> (MULQU2 x y)
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(Div128u xhi xlo y) -> (DIVQU2 xhi xlo y)
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@ -204,12 +204,8 @@ func init() {
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{name: "HMULQ", argLength: 2, reg: gp21hmul, asm: "IMULQ", clobberFlags: true}, // (arg0 * arg1) >> width
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{name: "HMULL", argLength: 2, reg: gp21hmul, asm: "IMULL", clobberFlags: true}, // (arg0 * arg1) >> width
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{name: "HMULW", argLength: 2, reg: gp21hmul, asm: "IMULW", clobberFlags: true}, // (arg0 * arg1) >> width
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{name: "HMULB", argLength: 2, reg: gp21hmul, asm: "IMULB", clobberFlags: true}, // (arg0 * arg1) >> width
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{name: "HMULQU", argLength: 2, reg: gp21hmul, asm: "MULQ", clobberFlags: true}, // (arg0 * arg1) >> width
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{name: "HMULLU", argLength: 2, reg: gp21hmul, asm: "MULL", clobberFlags: true}, // (arg0 * arg1) >> width
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{name: "HMULWU", argLength: 2, reg: gp21hmul, asm: "MULW", clobberFlags: true}, // (arg0 * arg1) >> width
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{name: "HMULBU", argLength: 2, reg: gp21hmul, asm: "MULB", clobberFlags: true}, // (arg0 * arg1) >> width
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{name: "AVGQU", argLength: 2, reg: gp21, commutative: true, resultInArg0: true, clobberFlags: true}, // (arg0 + arg1) / 2 as unsigned, all 64 result bits
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@ -30,10 +30,6 @@
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(Hmul32 x y) -> (HMUL x y)
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(Hmul32u x y) -> (HMULU x y)
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(Hmul16 x y) -> (SRAconst (MUL <config.fe.TypeInt32()> (SignExt16to32 x) (SignExt16to32 y)) [16])
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(Hmul16u x y) -> (SRLconst (MUL <config.fe.TypeUInt32()> (ZeroExt16to32 x) (ZeroExt16to32 y)) [16])
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(Hmul8 x y) -> (SRAconst (MUL <config.fe.TypeInt16()> (SignExt8to32 x) (SignExt8to32 y)) [8])
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(Hmul8u x y) -> (SRLconst (MUL <config.fe.TypeUInt16()> (ZeroExt8to32 x) (ZeroExt8to32 y)) [8])
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(Mul32uhilo x y) -> (MULLU x y)
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@ -29,10 +29,6 @@
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(Hmul64u x y) -> (UMULH x y)
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(Hmul32 x y) -> (SRAconst (MULL <config.fe.TypeInt64()> x y) [32])
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(Hmul32u x y) -> (SRAconst (UMULL <config.fe.TypeUInt64()> x y) [32])
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(Hmul16 x y) -> (SRAconst (MULW <config.fe.TypeInt32()> (SignExt16to32 x) (SignExt16to32 y)) [16])
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(Hmul16u x y) -> (SRLconst (MUL <config.fe.TypeUInt32()> (ZeroExt16to32 x) (ZeroExt16to32 y)) [16])
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(Hmul8 x y) -> (SRAconst (MULW <config.fe.TypeInt16()> (SignExt8to32 x) (SignExt8to32 y)) [8])
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(Hmul8u x y) -> (SRLconst (MUL <config.fe.TypeUInt16()> (ZeroExt8to32 x) (ZeroExt8to32 y)) [8])
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(Div64 x y) -> (DIV x y)
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(Div64u x y) -> (UDIV x y)
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@ -32,10 +32,6 @@
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(Hmul32 x y) -> (Select0 (MULT x y))
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(Hmul32u x y) -> (Select0 (MULTU x y))
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(Hmul16 x y) -> (SRAconst (MUL <config.fe.TypeInt32()> (SignExt16to32 x) (SignExt16to32 y)) [16])
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(Hmul16u x y) -> (SRLconst (MUL <config.fe.TypeUInt32()> (ZeroExt16to32 x) (ZeroExt16to32 y)) [16])
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(Hmul8 x y) -> (SRAconst (MUL <config.fe.TypeInt32()> (SignExt8to32 x) (SignExt8to32 y)) [8])
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(Hmul8u x y) -> (SRLconst (MUL <config.fe.TypeUInt32()> (ZeroExt8to32 x) (ZeroExt8to32 y)) [8])
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(Mul32uhilo x y) -> (MULTU x y)
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@ -29,10 +29,6 @@
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(Hmul64u x y) -> (Select0 (MULVU x y))
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(Hmul32 x y) -> (SRAVconst (Select1 <config.fe.TypeInt64()> (MULV (SignExt32to64 x) (SignExt32to64 y))) [32])
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(Hmul32u x y) -> (SRLVconst (Select1 <config.fe.TypeUInt64()> (MULVU (ZeroExt32to64 x) (ZeroExt32to64 y))) [32])
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(Hmul16 x y) -> (SRAVconst (Select1 <config.fe.TypeInt32()> (MULV (SignExt16to64 x) (SignExt16to64 y))) [16])
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(Hmul16u x y) -> (SRLVconst (Select1 <config.fe.TypeUInt32()> (MULVU (ZeroExt16to64 x) (ZeroExt16to64 y))) [16])
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(Hmul8 x y) -> (SRAVconst (Select1 <config.fe.TypeInt16()> (MULV (SignExt8to64 x) (SignExt8to64 y))) [8])
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(Hmul8u x y) -> (SRLVconst (Select1 <config.fe.TypeUInt16()> (MULVU (ZeroExt8to64 x) (ZeroExt8to64 y))) [8])
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(Div64 x y) -> (Select1 (DIVV x y))
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(Div64u x y) -> (Select1 (DIVVU x y))
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@ -49,10 +49,6 @@
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(Hmul64u x y) -> (MULHDU x y)
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(Hmul32 x y) -> (MULHW x y)
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(Hmul32u x y) -> (MULHWU x y)
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(Hmul16 x y) -> (SRAWconst (MULLW <config.fe.TypeInt32()> (SignExt16to32 x) (SignExt16to32 y)) [16])
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(Hmul16u x y) -> (SRWconst (MULLW <config.fe.TypeUInt32()> (ZeroExt16to32 x) (ZeroExt16to32 y)) [16])
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(Hmul8 x y) -> (SRAWconst (MULLW <config.fe.TypeInt16()> (SignExt8to32 x) (SignExt8to32 y)) [8])
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(Hmul8u x y) -> (SRWconst (MULLW <config.fe.TypeUInt16()> (ZeroExt8to32 x) (ZeroExt8to32 y)) [8])
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(Mul32F x y) -> (FMULS x y)
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(Mul64F x y) -> (FMUL x y)
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@ -44,10 +44,6 @@
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(Hmul64u x y) -> (MULHDU x y)
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(Hmul32 x y) -> (SRDconst [32] (MULLD (MOVWreg x) (MOVWreg y)))
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(Hmul32u x y) -> (SRDconst [32] (MULLD (MOVWZreg x) (MOVWZreg y)))
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(Hmul16 x y) -> (SRDconst [16] (MULLW (MOVHreg x) (MOVHreg y)))
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(Hmul16u x y) -> (SRDconst [16] (MULLW (MOVHZreg x) (MOVHZreg y)))
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(Hmul8 x y) -> (SRDconst [8] (MULLW (MOVBreg x) (MOVBreg y)))
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(Hmul8u x y) -> (SRDconst [8] (MULLW (MOVBZreg x) (MOVBZreg y)))
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(Mod64 x y) -> (MODD x y)
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(Mod64u x y) -> (MODDU x y)
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@ -49,10 +49,6 @@ var genericOps = []opData{
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{name: "Div32F", argLength: 2}, // arg0 / arg1
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{name: "Div64F", argLength: 2},
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{name: "Hmul8", argLength: 2}, // (arg0 * arg1) >> width, signed
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{name: "Hmul8u", argLength: 2}, // (arg0 * arg1) >> width, unsigned
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{name: "Hmul16", argLength: 2},
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{name: "Hmul16u", argLength: 2},
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{name: "Hmul32", argLength: 2},
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{name: "Hmul32u", argLength: 2},
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{name: "Hmul64", argLength: 2},
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@ -268,10 +268,6 @@ const (
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Op386MULLconst
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Op386HMULL
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Op386HMULLU
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Op386HMULW
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Op386HMULB
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Op386HMULWU
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Op386HMULBU
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Op386MULLQU
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Op386AVGLU
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Op386DIVL
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@ -454,12 +450,8 @@ const (
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OpAMD64MULLconst
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OpAMD64HMULQ
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OpAMD64HMULL
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OpAMD64HMULW
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OpAMD64HMULB
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OpAMD64HMULQU
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OpAMD64HMULLU
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OpAMD64HMULWU
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OpAMD64HMULBU
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OpAMD64AVGQU
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OpAMD64DIVQ
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OpAMD64DIVL
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@ -1625,10 +1617,6 @@ const (
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OpMul64F
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OpDiv32F
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OpDiv64F
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OpHmul8
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OpHmul8u
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OpHmul16
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OpHmul16u
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OpHmul32
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OpHmul32u
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OpHmul64
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@ -2509,70 +2497,6 @@ var opcodeTable = [...]opInfo{
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},
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},
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},
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{
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name: "HMULW",
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argLen: 2,
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clobberFlags: true,
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asm: x86.AIMULW,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 1}, // AX
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{1, 255}, // AX CX DX BX SP BP SI DI
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},
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clobbers: 1, // AX
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outputs: []outputInfo{
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{0, 4}, // DX
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},
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},
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},
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{
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name: "HMULB",
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argLen: 2,
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clobberFlags: true,
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asm: x86.AIMULB,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 1}, // AX
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{1, 255}, // AX CX DX BX SP BP SI DI
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},
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clobbers: 1, // AX
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outputs: []outputInfo{
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{0, 4}, // DX
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},
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},
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},
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{
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name: "HMULWU",
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argLen: 2,
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clobberFlags: true,
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asm: x86.AMULW,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 1}, // AX
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{1, 255}, // AX CX DX BX SP BP SI DI
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},
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clobbers: 1, // AX
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outputs: []outputInfo{
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{0, 4}, // DX
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},
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},
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},
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{
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name: "HMULBU",
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argLen: 2,
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clobberFlags: true,
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asm: x86.AMULB,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 1}, // AX
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{1, 255}, // AX CX DX BX SP BP SI DI
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},
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clobbers: 1, // AX
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outputs: []outputInfo{
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{0, 4}, // DX
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},
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},
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},
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{
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name: "MULLQU",
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argLen: 2,
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@ -5017,38 +4941,6 @@ var opcodeTable = [...]opInfo{
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},
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},
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},
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{
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name: "HMULW",
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argLen: 2,
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clobberFlags: true,
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asm: x86.AIMULW,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 1}, // AX
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{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
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},
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clobbers: 1, // AX
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outputs: []outputInfo{
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{0, 4}, // DX
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},
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},
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},
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{
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name: "HMULB",
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argLen: 2,
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clobberFlags: true,
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asm: x86.AIMULB,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 1}, // AX
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{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
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},
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clobbers: 1, // AX
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outputs: []outputInfo{
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{0, 4}, // DX
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},
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},
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},
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{
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name: "HMULQU",
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argLen: 2,
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@ -5081,38 +4973,6 @@ var opcodeTable = [...]opInfo{
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},
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},
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},
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{
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name: "HMULWU",
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argLen: 2,
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clobberFlags: true,
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asm: x86.AMULW,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 1}, // AX
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{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
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},
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clobbers: 1, // AX
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outputs: []outputInfo{
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{0, 4}, // DX
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},
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},
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},
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{
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name: "HMULBU",
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argLen: 2,
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clobberFlags: true,
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asm: x86.AMULB,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 1}, // AX
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{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
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},
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clobbers: 1, // AX
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outputs: []outputInfo{
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{0, 4}, // DX
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},
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},
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},
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{
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name: "AVGQU",
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argLen: 2,
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@ -20619,26 +20479,6 @@ var opcodeTable = [...]opInfo{
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argLen: 2,
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generic: true,
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},
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{
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name: "Hmul8",
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argLen: 2,
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generic: true,
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},
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{
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name: "Hmul8u",
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argLen: 2,
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generic: true,
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},
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{
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name: "Hmul16",
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argLen: 2,
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generic: true,
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},
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{
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name: "Hmul16u",
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argLen: 2,
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generic: true,
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},
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{
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name: "Hmul32",
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argLen: 2,
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@ -346,18 +346,10 @@ func rewriteValue386(v *Value, config *Config) bool {
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return rewriteValue386_OpGreater8(v, config)
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case OpGreater8U:
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return rewriteValue386_OpGreater8U(v, config)
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case OpHmul16:
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return rewriteValue386_OpHmul16(v, config)
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case OpHmul16u:
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return rewriteValue386_OpHmul16u(v, config)
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case OpHmul32:
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return rewriteValue386_OpHmul32(v, config)
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case OpHmul32u:
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return rewriteValue386_OpHmul32u(v, config)
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case OpHmul8:
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return rewriteValue386_OpHmul8(v, config)
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case OpHmul8u:
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return rewriteValue386_OpHmul8u(v, config)
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case OpInterCall:
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return rewriteValue386_OpInterCall(v, config)
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case OpIsInBounds:
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@ -10564,36 +10556,6 @@ func rewriteValue386_OpGreater8U(v *Value, config *Config) bool {
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return true
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}
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}
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func rewriteValue386_OpHmul16(v *Value, config *Config) bool {
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b := v.Block
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_ = b
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// match: (Hmul16 x y)
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// cond:
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// result: (HMULW x y)
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for {
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x := v.Args[0]
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y := v.Args[1]
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v.reset(Op386HMULW)
|
||||
v.AddArg(x)
|
||||
v.AddArg(y)
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValue386_OpHmul16u(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (Hmul16u x y)
|
||||
// cond:
|
||||
// result: (HMULWU x y)
|
||||
for {
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.reset(Op386HMULWU)
|
||||
v.AddArg(x)
|
||||
v.AddArg(y)
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValue386_OpHmul32(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
@ -10624,36 +10586,6 @@ func rewriteValue386_OpHmul32u(v *Value, config *Config) bool {
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValue386_OpHmul8(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (Hmul8 x y)
|
||||
// cond:
|
||||
// result: (HMULB x y)
|
||||
for {
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.reset(Op386HMULB)
|
||||
v.AddArg(x)
|
||||
v.AddArg(y)
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValue386_OpHmul8u(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (Hmul8u x y)
|
||||
// cond:
|
||||
// result: (HMULBU x y)
|
||||
for {
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.reset(Op386HMULBU)
|
||||
v.AddArg(x)
|
||||
v.AddArg(y)
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValue386_OpInterCall(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
|
@ -512,10 +512,6 @@ func rewriteValueAMD64(v *Value, config *Config) bool {
|
||||
return rewriteValueAMD64_OpGreater8(v, config)
|
||||
case OpGreater8U:
|
||||
return rewriteValueAMD64_OpGreater8U(v, config)
|
||||
case OpHmul16:
|
||||
return rewriteValueAMD64_OpHmul16(v, config)
|
||||
case OpHmul16u:
|
||||
return rewriteValueAMD64_OpHmul16u(v, config)
|
||||
case OpHmul32:
|
||||
return rewriteValueAMD64_OpHmul32(v, config)
|
||||
case OpHmul32u:
|
||||
@ -524,10 +520,6 @@ func rewriteValueAMD64(v *Value, config *Config) bool {
|
||||
return rewriteValueAMD64_OpHmul64(v, config)
|
||||
case OpHmul64u:
|
||||
return rewriteValueAMD64_OpHmul64u(v, config)
|
||||
case OpHmul8:
|
||||
return rewriteValueAMD64_OpHmul8(v, config)
|
||||
case OpHmul8u:
|
||||
return rewriteValueAMD64_OpHmul8u(v, config)
|
||||
case OpInt64Hi:
|
||||
return rewriteValueAMD64_OpInt64Hi(v, config)
|
||||
case OpInterCall:
|
||||
@ -18834,36 +18826,6 @@ func rewriteValueAMD64_OpGreater8U(v *Value, config *Config) bool {
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValueAMD64_OpHmul16(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (Hmul16 x y)
|
||||
// cond:
|
||||
// result: (HMULW x y)
|
||||
for {
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.reset(OpAMD64HMULW)
|
||||
v.AddArg(x)
|
||||
v.AddArg(y)
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValueAMD64_OpHmul16u(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (Hmul16u x y)
|
||||
// cond:
|
||||
// result: (HMULWU x y)
|
||||
for {
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.reset(OpAMD64HMULWU)
|
||||
v.AddArg(x)
|
||||
v.AddArg(y)
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValueAMD64_OpHmul32(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
@ -18924,36 +18886,6 @@ func rewriteValueAMD64_OpHmul64u(v *Value, config *Config) bool {
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValueAMD64_OpHmul8(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (Hmul8 x y)
|
||||
// cond:
|
||||
// result: (HMULB x y)
|
||||
for {
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.reset(OpAMD64HMULB)
|
||||
v.AddArg(x)
|
||||
v.AddArg(y)
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValueAMD64_OpHmul8u(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (Hmul8u x y)
|
||||
// cond:
|
||||
// result: (HMULBU x y)
|
||||
for {
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.reset(OpAMD64HMULBU)
|
||||
v.AddArg(x)
|
||||
v.AddArg(y)
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValueAMD64_OpInt64Hi(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
|
@ -478,18 +478,10 @@ func rewriteValueARM(v *Value, config *Config) bool {
|
||||
return rewriteValueARM_OpGreater8(v, config)
|
||||
case OpGreater8U:
|
||||
return rewriteValueARM_OpGreater8U(v, config)
|
||||
case OpHmul16:
|
||||
return rewriteValueARM_OpHmul16(v, config)
|
||||
case OpHmul16u:
|
||||
return rewriteValueARM_OpHmul16u(v, config)
|
||||
case OpHmul32:
|
||||
return rewriteValueARM_OpHmul32(v, config)
|
||||
case OpHmul32u:
|
||||
return rewriteValueARM_OpHmul32u(v, config)
|
||||
case OpHmul8:
|
||||
return rewriteValueARM_OpHmul8(v, config)
|
||||
case OpHmul8u:
|
||||
return rewriteValueARM_OpHmul8u(v, config)
|
||||
case OpInterCall:
|
||||
return rewriteValueARM_OpInterCall(v, config)
|
||||
case OpIsInBounds:
|
||||
@ -14046,50 +14038,6 @@ func rewriteValueARM_OpGreater8U(v *Value, config *Config) bool {
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValueARM_OpHmul16(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (Hmul16 x y)
|
||||
// cond:
|
||||
// result: (SRAconst (MUL <config.fe.TypeInt32()> (SignExt16to32 x) (SignExt16to32 y)) [16])
|
||||
for {
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.reset(OpARMSRAconst)
|
||||
v.AuxInt = 16
|
||||
v0 := b.NewValue0(v.Pos, OpARMMUL, config.fe.TypeInt32())
|
||||
v1 := b.NewValue0(v.Pos, OpSignExt16to32, config.fe.TypeInt32())
|
||||
v1.AddArg(x)
|
||||
v0.AddArg(v1)
|
||||
v2 := b.NewValue0(v.Pos, OpSignExt16to32, config.fe.TypeInt32())
|
||||
v2.AddArg(y)
|
||||
v0.AddArg(v2)
|
||||
v.AddArg(v0)
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValueARM_OpHmul16u(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (Hmul16u x y)
|
||||
// cond:
|
||||
// result: (SRLconst (MUL <config.fe.TypeUInt32()> (ZeroExt16to32 x) (ZeroExt16to32 y)) [16])
|
||||
for {
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.reset(OpARMSRLconst)
|
||||
v.AuxInt = 16
|
||||
v0 := b.NewValue0(v.Pos, OpARMMUL, config.fe.TypeUInt32())
|
||||
v1 := b.NewValue0(v.Pos, OpZeroExt16to32, config.fe.TypeUInt32())
|
||||
v1.AddArg(x)
|
||||
v0.AddArg(v1)
|
||||
v2 := b.NewValue0(v.Pos, OpZeroExt16to32, config.fe.TypeUInt32())
|
||||
v2.AddArg(y)
|
||||
v0.AddArg(v2)
|
||||
v.AddArg(v0)
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValueARM_OpHmul32(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
@ -14120,50 +14068,6 @@ func rewriteValueARM_OpHmul32u(v *Value, config *Config) bool {
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValueARM_OpHmul8(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (Hmul8 x y)
|
||||
// cond:
|
||||
// result: (SRAconst (MUL <config.fe.TypeInt16()> (SignExt8to32 x) (SignExt8to32 y)) [8])
|
||||
for {
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.reset(OpARMSRAconst)
|
||||
v.AuxInt = 8
|
||||
v0 := b.NewValue0(v.Pos, OpARMMUL, config.fe.TypeInt16())
|
||||
v1 := b.NewValue0(v.Pos, OpSignExt8to32, config.fe.TypeInt32())
|
||||
v1.AddArg(x)
|
||||
v0.AddArg(v1)
|
||||
v2 := b.NewValue0(v.Pos, OpSignExt8to32, config.fe.TypeInt32())
|
||||
v2.AddArg(y)
|
||||
v0.AddArg(v2)
|
||||
v.AddArg(v0)
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValueARM_OpHmul8u(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (Hmul8u x y)
|
||||
// cond:
|
||||
// result: (SRLconst (MUL <config.fe.TypeUInt16()> (ZeroExt8to32 x) (ZeroExt8to32 y)) [8])
|
||||
for {
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.reset(OpARMSRLconst)
|
||||
v.AuxInt = 8
|
||||
v0 := b.NewValue0(v.Pos, OpARMMUL, config.fe.TypeUInt16())
|
||||
v1 := b.NewValue0(v.Pos, OpZeroExt8to32, config.fe.TypeUInt32())
|
||||
v1.AddArg(x)
|
||||
v0.AddArg(v1)
|
||||
v2 := b.NewValue0(v.Pos, OpZeroExt8to32, config.fe.TypeUInt32())
|
||||
v2.AddArg(y)
|
||||
v0.AddArg(v2)
|
||||
v.AddArg(v0)
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValueARM_OpInterCall(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
|
@ -404,10 +404,6 @@ func rewriteValueARM64(v *Value, config *Config) bool {
|
||||
return rewriteValueARM64_OpGreater8(v, config)
|
||||
case OpGreater8U:
|
||||
return rewriteValueARM64_OpGreater8U(v, config)
|
||||
case OpHmul16:
|
||||
return rewriteValueARM64_OpHmul16(v, config)
|
||||
case OpHmul16u:
|
||||
return rewriteValueARM64_OpHmul16u(v, config)
|
||||
case OpHmul32:
|
||||
return rewriteValueARM64_OpHmul32(v, config)
|
||||
case OpHmul32u:
|
||||
@ -416,10 +412,6 @@ func rewriteValueARM64(v *Value, config *Config) bool {
|
||||
return rewriteValueARM64_OpHmul64(v, config)
|
||||
case OpHmul64u:
|
||||
return rewriteValueARM64_OpHmul64u(v, config)
|
||||
case OpHmul8:
|
||||
return rewriteValueARM64_OpHmul8(v, config)
|
||||
case OpHmul8u:
|
||||
return rewriteValueARM64_OpHmul8u(v, config)
|
||||
case OpInterCall:
|
||||
return rewriteValueARM64_OpInterCall(v, config)
|
||||
case OpIsInBounds:
|
||||
@ -10875,50 +10867,6 @@ func rewriteValueARM64_OpGreater8U(v *Value, config *Config) bool {
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValueARM64_OpHmul16(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (Hmul16 x y)
|
||||
// cond:
|
||||
// result: (SRAconst (MULW <config.fe.TypeInt32()> (SignExt16to32 x) (SignExt16to32 y)) [16])
|
||||
for {
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.reset(OpARM64SRAconst)
|
||||
v.AuxInt = 16
|
||||
v0 := b.NewValue0(v.Pos, OpARM64MULW, config.fe.TypeInt32())
|
||||
v1 := b.NewValue0(v.Pos, OpSignExt16to32, config.fe.TypeInt32())
|
||||
v1.AddArg(x)
|
||||
v0.AddArg(v1)
|
||||
v2 := b.NewValue0(v.Pos, OpSignExt16to32, config.fe.TypeInt32())
|
||||
v2.AddArg(y)
|
||||
v0.AddArg(v2)
|
||||
v.AddArg(v0)
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValueARM64_OpHmul16u(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (Hmul16u x y)
|
||||
// cond:
|
||||
// result: (SRLconst (MUL <config.fe.TypeUInt32()> (ZeroExt16to32 x) (ZeroExt16to32 y)) [16])
|
||||
for {
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.reset(OpARM64SRLconst)
|
||||
v.AuxInt = 16
|
||||
v0 := b.NewValue0(v.Pos, OpARM64MUL, config.fe.TypeUInt32())
|
||||
v1 := b.NewValue0(v.Pos, OpZeroExt16to32, config.fe.TypeUInt32())
|
||||
v1.AddArg(x)
|
||||
v0.AddArg(v1)
|
||||
v2 := b.NewValue0(v.Pos, OpZeroExt16to32, config.fe.TypeUInt32())
|
||||
v2.AddArg(y)
|
||||
v0.AddArg(v2)
|
||||
v.AddArg(v0)
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValueARM64_OpHmul32(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
@ -10985,50 +10933,6 @@ func rewriteValueARM64_OpHmul64u(v *Value, config *Config) bool {
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValueARM64_OpHmul8(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (Hmul8 x y)
|
||||
// cond:
|
||||
// result: (SRAconst (MULW <config.fe.TypeInt16()> (SignExt8to32 x) (SignExt8to32 y)) [8])
|
||||
for {
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.reset(OpARM64SRAconst)
|
||||
v.AuxInt = 8
|
||||
v0 := b.NewValue0(v.Pos, OpARM64MULW, config.fe.TypeInt16())
|
||||
v1 := b.NewValue0(v.Pos, OpSignExt8to32, config.fe.TypeInt32())
|
||||
v1.AddArg(x)
|
||||
v0.AddArg(v1)
|
||||
v2 := b.NewValue0(v.Pos, OpSignExt8to32, config.fe.TypeInt32())
|
||||
v2.AddArg(y)
|
||||
v0.AddArg(v2)
|
||||
v.AddArg(v0)
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValueARM64_OpHmul8u(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (Hmul8u x y)
|
||||
// cond:
|
||||
// result: (SRLconst (MUL <config.fe.TypeUInt16()> (ZeroExt8to32 x) (ZeroExt8to32 y)) [8])
|
||||
for {
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.reset(OpARM64SRLconst)
|
||||
v.AuxInt = 8
|
||||
v0 := b.NewValue0(v.Pos, OpARM64MUL, config.fe.TypeUInt16())
|
||||
v1 := b.NewValue0(v.Pos, OpZeroExt8to32, config.fe.TypeUInt32())
|
||||
v1.AddArg(x)
|
||||
v0.AddArg(v1)
|
||||
v2 := b.NewValue0(v.Pos, OpZeroExt8to32, config.fe.TypeUInt32())
|
||||
v2.AddArg(y)
|
||||
v0.AddArg(v2)
|
||||
v.AddArg(v0)
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValueARM64_OpInterCall(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
|
@ -158,18 +158,10 @@ func rewriteValueMIPS(v *Value, config *Config) bool {
|
||||
return rewriteValueMIPS_OpGreater8(v, config)
|
||||
case OpGreater8U:
|
||||
return rewriteValueMIPS_OpGreater8U(v, config)
|
||||
case OpHmul16:
|
||||
return rewriteValueMIPS_OpHmul16(v, config)
|
||||
case OpHmul16u:
|
||||
return rewriteValueMIPS_OpHmul16u(v, config)
|
||||
case OpHmul32:
|
||||
return rewriteValueMIPS_OpHmul32(v, config)
|
||||
case OpHmul32u:
|
||||
return rewriteValueMIPS_OpHmul32u(v, config)
|
||||
case OpHmul8:
|
||||
return rewriteValueMIPS_OpHmul8(v, config)
|
||||
case OpHmul8u:
|
||||
return rewriteValueMIPS_OpHmul8u(v, config)
|
||||
case OpInterCall:
|
||||
return rewriteValueMIPS_OpInterCall(v, config)
|
||||
case OpIsInBounds:
|
||||
@ -1909,50 +1901,6 @@ func rewriteValueMIPS_OpGreater8U(v *Value, config *Config) bool {
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValueMIPS_OpHmul16(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (Hmul16 x y)
|
||||
// cond:
|
||||
// result: (SRAconst (MUL <config.fe.TypeInt32()> (SignExt16to32 x) (SignExt16to32 y)) [16])
|
||||
for {
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.reset(OpMIPSSRAconst)
|
||||
v.AuxInt = 16
|
||||
v0 := b.NewValue0(v.Pos, OpMIPSMUL, config.fe.TypeInt32())
|
||||
v1 := b.NewValue0(v.Pos, OpSignExt16to32, config.fe.TypeInt32())
|
||||
v1.AddArg(x)
|
||||
v0.AddArg(v1)
|
||||
v2 := b.NewValue0(v.Pos, OpSignExt16to32, config.fe.TypeInt32())
|
||||
v2.AddArg(y)
|
||||
v0.AddArg(v2)
|
||||
v.AddArg(v0)
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValueMIPS_OpHmul16u(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (Hmul16u x y)
|
||||
// cond:
|
||||
// result: (SRLconst (MUL <config.fe.TypeUInt32()> (ZeroExt16to32 x) (ZeroExt16to32 y)) [16])
|
||||
for {
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.reset(OpMIPSSRLconst)
|
||||
v.AuxInt = 16
|
||||
v0 := b.NewValue0(v.Pos, OpMIPSMUL, config.fe.TypeUInt32())
|
||||
v1 := b.NewValue0(v.Pos, OpZeroExt16to32, config.fe.TypeUInt32())
|
||||
v1.AddArg(x)
|
||||
v0.AddArg(v1)
|
||||
v2 := b.NewValue0(v.Pos, OpZeroExt16to32, config.fe.TypeUInt32())
|
||||
v2.AddArg(y)
|
||||
v0.AddArg(v2)
|
||||
v.AddArg(v0)
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValueMIPS_OpHmul32(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
@ -1987,50 +1935,6 @@ func rewriteValueMIPS_OpHmul32u(v *Value, config *Config) bool {
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValueMIPS_OpHmul8(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (Hmul8 x y)
|
||||
// cond:
|
||||
// result: (SRAconst (MUL <config.fe.TypeInt32()> (SignExt8to32 x) (SignExt8to32 y)) [8])
|
||||
for {
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.reset(OpMIPSSRAconst)
|
||||
v.AuxInt = 8
|
||||
v0 := b.NewValue0(v.Pos, OpMIPSMUL, config.fe.TypeInt32())
|
||||
v1 := b.NewValue0(v.Pos, OpSignExt8to32, config.fe.TypeInt32())
|
||||
v1.AddArg(x)
|
||||
v0.AddArg(v1)
|
||||
v2 := b.NewValue0(v.Pos, OpSignExt8to32, config.fe.TypeInt32())
|
||||
v2.AddArg(y)
|
||||
v0.AddArg(v2)
|
||||
v.AddArg(v0)
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValueMIPS_OpHmul8u(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (Hmul8u x y)
|
||||
// cond:
|
||||
// result: (SRLconst (MUL <config.fe.TypeUInt32()> (ZeroExt8to32 x) (ZeroExt8to32 y)) [8])
|
||||
for {
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.reset(OpMIPSSRLconst)
|
||||
v.AuxInt = 8
|
||||
v0 := b.NewValue0(v.Pos, OpMIPSMUL, config.fe.TypeUInt32())
|
||||
v1 := b.NewValue0(v.Pos, OpZeroExt8to32, config.fe.TypeUInt32())
|
||||
v1.AddArg(x)
|
||||
v0.AddArg(v1)
|
||||
v2 := b.NewValue0(v.Pos, OpZeroExt8to32, config.fe.TypeUInt32())
|
||||
v2.AddArg(y)
|
||||
v0.AddArg(v2)
|
||||
v.AddArg(v0)
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValueMIPS_OpInterCall(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
|
@ -166,10 +166,6 @@ func rewriteValueMIPS64(v *Value, config *Config) bool {
|
||||
return rewriteValueMIPS64_OpGreater8(v, config)
|
||||
case OpGreater8U:
|
||||
return rewriteValueMIPS64_OpGreater8U(v, config)
|
||||
case OpHmul16:
|
||||
return rewriteValueMIPS64_OpHmul16(v, config)
|
||||
case OpHmul16u:
|
||||
return rewriteValueMIPS64_OpHmul16u(v, config)
|
||||
case OpHmul32:
|
||||
return rewriteValueMIPS64_OpHmul32(v, config)
|
||||
case OpHmul32u:
|
||||
@ -178,10 +174,6 @@ func rewriteValueMIPS64(v *Value, config *Config) bool {
|
||||
return rewriteValueMIPS64_OpHmul64(v, config)
|
||||
case OpHmul64u:
|
||||
return rewriteValueMIPS64_OpHmul64u(v, config)
|
||||
case OpHmul8:
|
||||
return rewriteValueMIPS64_OpHmul8(v, config)
|
||||
case OpHmul8u:
|
||||
return rewriteValueMIPS64_OpHmul8u(v, config)
|
||||
case OpInterCall:
|
||||
return rewriteValueMIPS64_OpInterCall(v, config)
|
||||
case OpIsInBounds:
|
||||
@ -1918,54 +1910,6 @@ func rewriteValueMIPS64_OpGreater8U(v *Value, config *Config) bool {
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValueMIPS64_OpHmul16(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (Hmul16 x y)
|
||||
// cond:
|
||||
// result: (SRAVconst (Select1 <config.fe.TypeInt32()> (MULV (SignExt16to64 x) (SignExt16to64 y))) [16])
|
||||
for {
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.reset(OpMIPS64SRAVconst)
|
||||
v.AuxInt = 16
|
||||
v0 := b.NewValue0(v.Pos, OpSelect1, config.fe.TypeInt32())
|
||||
v1 := b.NewValue0(v.Pos, OpMIPS64MULV, MakeTuple(config.fe.TypeInt64(), config.fe.TypeInt64()))
|
||||
v2 := b.NewValue0(v.Pos, OpSignExt16to64, config.fe.TypeInt64())
|
||||
v2.AddArg(x)
|
||||
v1.AddArg(v2)
|
||||
v3 := b.NewValue0(v.Pos, OpSignExt16to64, config.fe.TypeInt64())
|
||||
v3.AddArg(y)
|
||||
v1.AddArg(v3)
|
||||
v0.AddArg(v1)
|
||||
v.AddArg(v0)
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValueMIPS64_OpHmul16u(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (Hmul16u x y)
|
||||
// cond:
|
||||
// result: (SRLVconst (Select1 <config.fe.TypeUInt32()> (MULVU (ZeroExt16to64 x) (ZeroExt16to64 y))) [16])
|
||||
for {
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.reset(OpMIPS64SRLVconst)
|
||||
v.AuxInt = 16
|
||||
v0 := b.NewValue0(v.Pos, OpSelect1, config.fe.TypeUInt32())
|
||||
v1 := b.NewValue0(v.Pos, OpMIPS64MULVU, MakeTuple(config.fe.TypeUInt64(), config.fe.TypeUInt64()))
|
||||
v2 := b.NewValue0(v.Pos, OpZeroExt16to64, config.fe.TypeUInt64())
|
||||
v2.AddArg(x)
|
||||
v1.AddArg(v2)
|
||||
v3 := b.NewValue0(v.Pos, OpZeroExt16to64, config.fe.TypeUInt64())
|
||||
v3.AddArg(y)
|
||||
v1.AddArg(v3)
|
||||
v0.AddArg(v1)
|
||||
v.AddArg(v0)
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValueMIPS64_OpHmul32(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
@ -2048,54 +1992,6 @@ func rewriteValueMIPS64_OpHmul64u(v *Value, config *Config) bool {
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValueMIPS64_OpHmul8(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (Hmul8 x y)
|
||||
// cond:
|
||||
// result: (SRAVconst (Select1 <config.fe.TypeInt16()> (MULV (SignExt8to64 x) (SignExt8to64 y))) [8])
|
||||
for {
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.reset(OpMIPS64SRAVconst)
|
||||
v.AuxInt = 8
|
||||
v0 := b.NewValue0(v.Pos, OpSelect1, config.fe.TypeInt16())
|
||||
v1 := b.NewValue0(v.Pos, OpMIPS64MULV, MakeTuple(config.fe.TypeInt64(), config.fe.TypeInt64()))
|
||||
v2 := b.NewValue0(v.Pos, OpSignExt8to64, config.fe.TypeInt64())
|
||||
v2.AddArg(x)
|
||||
v1.AddArg(v2)
|
||||
v3 := b.NewValue0(v.Pos, OpSignExt8to64, config.fe.TypeInt64())
|
||||
v3.AddArg(y)
|
||||
v1.AddArg(v3)
|
||||
v0.AddArg(v1)
|
||||
v.AddArg(v0)
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValueMIPS64_OpHmul8u(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (Hmul8u x y)
|
||||
// cond:
|
||||
// result: (SRLVconst (Select1 <config.fe.TypeUInt16()> (MULVU (ZeroExt8to64 x) (ZeroExt8to64 y))) [8])
|
||||
for {
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.reset(OpMIPS64SRLVconst)
|
||||
v.AuxInt = 8
|
||||
v0 := b.NewValue0(v.Pos, OpSelect1, config.fe.TypeUInt16())
|
||||
v1 := b.NewValue0(v.Pos, OpMIPS64MULVU, MakeTuple(config.fe.TypeUInt64(), config.fe.TypeUInt64()))
|
||||
v2 := b.NewValue0(v.Pos, OpZeroExt8to64, config.fe.TypeUInt64())
|
||||
v2.AddArg(x)
|
||||
v1.AddArg(v2)
|
||||
v3 := b.NewValue0(v.Pos, OpZeroExt8to64, config.fe.TypeUInt64())
|
||||
v3.AddArg(y)
|
||||
v1.AddArg(v3)
|
||||
v0.AddArg(v1)
|
||||
v.AddArg(v0)
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValueMIPS64_OpInterCall(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
|
@ -192,10 +192,6 @@ func rewriteValuePPC64(v *Value, config *Config) bool {
|
||||
return rewriteValuePPC64_OpGreater8(v, config)
|
||||
case OpGreater8U:
|
||||
return rewriteValuePPC64_OpGreater8U(v, config)
|
||||
case OpHmul16:
|
||||
return rewriteValuePPC64_OpHmul16(v, config)
|
||||
case OpHmul16u:
|
||||
return rewriteValuePPC64_OpHmul16u(v, config)
|
||||
case OpHmul32:
|
||||
return rewriteValuePPC64_OpHmul32(v, config)
|
||||
case OpHmul32u:
|
||||
@ -204,10 +200,6 @@ func rewriteValuePPC64(v *Value, config *Config) bool {
|
||||
return rewriteValuePPC64_OpHmul64(v, config)
|
||||
case OpHmul64u:
|
||||
return rewriteValuePPC64_OpHmul64u(v, config)
|
||||
case OpHmul8:
|
||||
return rewriteValuePPC64_OpHmul8(v, config)
|
||||
case OpHmul8u:
|
||||
return rewriteValuePPC64_OpHmul8u(v, config)
|
||||
case OpInterCall:
|
||||
return rewriteValuePPC64_OpInterCall(v, config)
|
||||
case OpIsInBounds:
|
||||
@ -2151,50 +2143,6 @@ func rewriteValuePPC64_OpGreater8U(v *Value, config *Config) bool {
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValuePPC64_OpHmul16(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (Hmul16 x y)
|
||||
// cond:
|
||||
// result: (SRAWconst (MULLW <config.fe.TypeInt32()> (SignExt16to32 x) (SignExt16to32 y)) [16])
|
||||
for {
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.reset(OpPPC64SRAWconst)
|
||||
v.AuxInt = 16
|
||||
v0 := b.NewValue0(v.Pos, OpPPC64MULLW, config.fe.TypeInt32())
|
||||
v1 := b.NewValue0(v.Pos, OpSignExt16to32, config.fe.TypeInt32())
|
||||
v1.AddArg(x)
|
||||
v0.AddArg(v1)
|
||||
v2 := b.NewValue0(v.Pos, OpSignExt16to32, config.fe.TypeInt32())
|
||||
v2.AddArg(y)
|
||||
v0.AddArg(v2)
|
||||
v.AddArg(v0)
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValuePPC64_OpHmul16u(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (Hmul16u x y)
|
||||
// cond:
|
||||
// result: (SRWconst (MULLW <config.fe.TypeUInt32()> (ZeroExt16to32 x) (ZeroExt16to32 y)) [16])
|
||||
for {
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.reset(OpPPC64SRWconst)
|
||||
v.AuxInt = 16
|
||||
v0 := b.NewValue0(v.Pos, OpPPC64MULLW, config.fe.TypeUInt32())
|
||||
v1 := b.NewValue0(v.Pos, OpZeroExt16to32, config.fe.TypeUInt32())
|
||||
v1.AddArg(x)
|
||||
v0.AddArg(v1)
|
||||
v2 := b.NewValue0(v.Pos, OpZeroExt16to32, config.fe.TypeUInt32())
|
||||
v2.AddArg(y)
|
||||
v0.AddArg(v2)
|
||||
v.AddArg(v0)
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValuePPC64_OpHmul32(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
@ -2255,50 +2203,6 @@ func rewriteValuePPC64_OpHmul64u(v *Value, config *Config) bool {
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValuePPC64_OpHmul8(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (Hmul8 x y)
|
||||
// cond:
|
||||
// result: (SRAWconst (MULLW <config.fe.TypeInt16()> (SignExt8to32 x) (SignExt8to32 y)) [8])
|
||||
for {
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.reset(OpPPC64SRAWconst)
|
||||
v.AuxInt = 8
|
||||
v0 := b.NewValue0(v.Pos, OpPPC64MULLW, config.fe.TypeInt16())
|
||||
v1 := b.NewValue0(v.Pos, OpSignExt8to32, config.fe.TypeInt32())
|
||||
v1.AddArg(x)
|
||||
v0.AddArg(v1)
|
||||
v2 := b.NewValue0(v.Pos, OpSignExt8to32, config.fe.TypeInt32())
|
||||
v2.AddArg(y)
|
||||
v0.AddArg(v2)
|
||||
v.AddArg(v0)
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValuePPC64_OpHmul8u(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (Hmul8u x y)
|
||||
// cond:
|
||||
// result: (SRWconst (MULLW <config.fe.TypeUInt16()> (ZeroExt8to32 x) (ZeroExt8to32 y)) [8])
|
||||
for {
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.reset(OpPPC64SRWconst)
|
||||
v.AuxInt = 8
|
||||
v0 := b.NewValue0(v.Pos, OpPPC64MULLW, config.fe.TypeUInt16())
|
||||
v1 := b.NewValue0(v.Pos, OpZeroExt8to32, config.fe.TypeUInt32())
|
||||
v1.AddArg(x)
|
||||
v0.AddArg(v1)
|
||||
v2 := b.NewValue0(v.Pos, OpZeroExt8to32, config.fe.TypeUInt32())
|
||||
v2.AddArg(y)
|
||||
v0.AddArg(v2)
|
||||
v.AddArg(v0)
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValuePPC64_OpInterCall(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
|
@ -200,10 +200,6 @@ func rewriteValueS390X(v *Value, config *Config) bool {
|
||||
return rewriteValueS390X_OpGreater8(v, config)
|
||||
case OpGreater8U:
|
||||
return rewriteValueS390X_OpGreater8U(v, config)
|
||||
case OpHmul16:
|
||||
return rewriteValueS390X_OpHmul16(v, config)
|
||||
case OpHmul16u:
|
||||
return rewriteValueS390X_OpHmul16u(v, config)
|
||||
case OpHmul32:
|
||||
return rewriteValueS390X_OpHmul32(v, config)
|
||||
case OpHmul32u:
|
||||
@ -212,10 +208,6 @@ func rewriteValueS390X(v *Value, config *Config) bool {
|
||||
return rewriteValueS390X_OpHmul64(v, config)
|
||||
case OpHmul64u:
|
||||
return rewriteValueS390X_OpHmul64u(v, config)
|
||||
case OpHmul8:
|
||||
return rewriteValueS390X_OpHmul8(v, config)
|
||||
case OpHmul8u:
|
||||
return rewriteValueS390X_OpHmul8u(v, config)
|
||||
case OpITab:
|
||||
return rewriteValueS390X_OpITab(v, config)
|
||||
case OpInterCall:
|
||||
@ -2465,50 +2457,6 @@ func rewriteValueS390X_OpGreater8U(v *Value, config *Config) bool {
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValueS390X_OpHmul16(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (Hmul16 x y)
|
||||
// cond:
|
||||
// result: (SRDconst [16] (MULLW (MOVHreg x) (MOVHreg y)))
|
||||
for {
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.reset(OpS390XSRDconst)
|
||||
v.AuxInt = 16
|
||||
v0 := b.NewValue0(v.Pos, OpS390XMULLW, config.fe.TypeInt32())
|
||||
v1 := b.NewValue0(v.Pos, OpS390XMOVHreg, config.fe.TypeInt64())
|
||||
v1.AddArg(x)
|
||||
v0.AddArg(v1)
|
||||
v2 := b.NewValue0(v.Pos, OpS390XMOVHreg, config.fe.TypeInt64())
|
||||
v2.AddArg(y)
|
||||
v0.AddArg(v2)
|
||||
v.AddArg(v0)
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValueS390X_OpHmul16u(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (Hmul16u x y)
|
||||
// cond:
|
||||
// result: (SRDconst [16] (MULLW (MOVHZreg x) (MOVHZreg y)))
|
||||
for {
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.reset(OpS390XSRDconst)
|
||||
v.AuxInt = 16
|
||||
v0 := b.NewValue0(v.Pos, OpS390XMULLW, config.fe.TypeInt32())
|
||||
v1 := b.NewValue0(v.Pos, OpS390XMOVHZreg, config.fe.TypeUInt64())
|
||||
v1.AddArg(x)
|
||||
v0.AddArg(v1)
|
||||
v2 := b.NewValue0(v.Pos, OpS390XMOVHZreg, config.fe.TypeUInt64())
|
||||
v2.AddArg(y)
|
||||
v0.AddArg(v2)
|
||||
v.AddArg(v0)
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValueS390X_OpHmul32(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
@ -2583,50 +2531,6 @@ func rewriteValueS390X_OpHmul64u(v *Value, config *Config) bool {
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValueS390X_OpHmul8(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (Hmul8 x y)
|
||||
// cond:
|
||||
// result: (SRDconst [8] (MULLW (MOVBreg x) (MOVBreg y)))
|
||||
for {
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.reset(OpS390XSRDconst)
|
||||
v.AuxInt = 8
|
||||
v0 := b.NewValue0(v.Pos, OpS390XMULLW, config.fe.TypeInt32())
|
||||
v1 := b.NewValue0(v.Pos, OpS390XMOVBreg, config.fe.TypeInt64())
|
||||
v1.AddArg(x)
|
||||
v0.AddArg(v1)
|
||||
v2 := b.NewValue0(v.Pos, OpS390XMOVBreg, config.fe.TypeInt64())
|
||||
v2.AddArg(y)
|
||||
v0.AddArg(v2)
|
||||
v.AddArg(v0)
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValueS390X_OpHmul8u(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (Hmul8u x y)
|
||||
// cond:
|
||||
// result: (SRDconst [8] (MULLW (MOVBZreg x) (MOVBZreg y)))
|
||||
for {
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.reset(OpS390XSRDconst)
|
||||
v.AuxInt = 8
|
||||
v0 := b.NewValue0(v.Pos, OpS390XMULLW, config.fe.TypeInt32())
|
||||
v1 := b.NewValue0(v.Pos, OpS390XMOVBZreg, config.fe.TypeUInt64())
|
||||
v1.AddArg(x)
|
||||
v0.AddArg(v1)
|
||||
v2 := b.NewValue0(v.Pos, OpS390XMOVBZreg, config.fe.TypeUInt64())
|
||||
v2.AddArg(y)
|
||||
v0.AddArg(v2)
|
||||
v.AddArg(v0)
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValueS390X_OpITab(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
|
@ -264,8 +264,7 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
|
||||
j2.To.Val = s.Pc()
|
||||
}
|
||||
|
||||
case ssa.Op386HMULL, ssa.Op386HMULW, ssa.Op386HMULB,
|
||||
ssa.Op386HMULLU, ssa.Op386HMULWU, ssa.Op386HMULBU:
|
||||
case ssa.Op386HMULL, ssa.Op386HMULLU:
|
||||
// the frontend rewrites constant division by 8/16/32 bit integers into
|
||||
// HMUL by a constant
|
||||
// SSA rewrites generate the 64 bit versions
|
||||
|
Loading…
Reference in New Issue
Block a user