2011-11-10 17:08:28 -07:00
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// Created by cgo -cdefs - DO NOT EDIT
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2012-01-10 10:48:10 -07:00
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// cgo -cdefs defs_darwin.go
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2009-03-24 14:51:48 -06:00
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enum {
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2013-03-14 00:38:37 -06:00
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EINTR = 0x4,
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EFAULT = 0xe,
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2011-11-10 17:08:28 -07:00
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PROT_NONE = 0x0,
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PROT_READ = 0x1,
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PROT_WRITE = 0x2,
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PROT_EXEC = 0x4,
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MAP_ANON = 0x1000,
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MAP_PRIVATE = 0x2,
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MAP_FIXED = 0x10,
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2012-01-19 13:51:29 -07:00
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MADV_DONTNEED = 0x4,
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MADV_FREE = 0x5,
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MACH_MSG_TYPE_MOVE_RECEIVE = 0x10,
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MACH_MSG_TYPE_MOVE_SEND = 0x11,
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MACH_MSG_TYPE_MOVE_SEND_ONCE = 0x12,
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MACH_MSG_TYPE_COPY_SEND = 0x13,
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MACH_MSG_TYPE_MAKE_SEND = 0x14,
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MACH_MSG_TYPE_MAKE_SEND_ONCE = 0x15,
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MACH_MSG_TYPE_COPY_RECEIVE = 0x16,
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MACH_MSG_PORT_DESCRIPTOR = 0x0,
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MACH_MSG_OOL_DESCRIPTOR = 0x1,
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MACH_MSG_OOL_PORTS_DESCRIPTOR = 0x2,
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MACH_MSG_OOL_VOLATILE_DESCRIPTOR = 0x3,
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MACH_MSGH_BITS_COMPLEX = 0x80000000,
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MACH_SEND_MSG = 0x1,
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MACH_RCV_MSG = 0x2,
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MACH_RCV_LARGE = 0x4,
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MACH_SEND_TIMEOUT = 0x10,
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MACH_SEND_INTERRUPT = 0x40,
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MACH_SEND_ALWAYS = 0x10000,
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MACH_SEND_TRAILER = 0x20000,
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MACH_RCV_TIMEOUT = 0x100,
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MACH_RCV_NOTIFY = 0x200,
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MACH_RCV_INTERRUPT = 0x400,
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MACH_RCV_OVERWRITE = 0x1000,
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NDR_PROTOCOL_2_0 = 0x0,
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NDR_INT_BIG_ENDIAN = 0x0,
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NDR_INT_LITTLE_ENDIAN = 0x1,
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NDR_FLOAT_IEEE = 0x0,
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NDR_CHAR_ASCII = 0x0,
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SA_SIGINFO = 0x40,
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SA_RESTART = 0x2,
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SA_ONSTACK = 0x1,
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SA_USERTRAMP = 0x100,
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SA_64REGSET = 0x200,
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SIGHUP = 0x1,
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SIGINT = 0x2,
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SIGQUIT = 0x3,
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SIGILL = 0x4,
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SIGTRAP = 0x5,
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SIGABRT = 0x6,
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SIGEMT = 0x7,
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SIGFPE = 0x8,
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SIGKILL = 0x9,
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SIGBUS = 0xa,
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SIGSEGV = 0xb,
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SIGSYS = 0xc,
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SIGPIPE = 0xd,
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SIGALRM = 0xe,
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SIGTERM = 0xf,
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SIGURG = 0x10,
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SIGSTOP = 0x11,
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SIGTSTP = 0x12,
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SIGCONT = 0x13,
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SIGCHLD = 0x14,
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SIGTTIN = 0x15,
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SIGTTOU = 0x16,
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SIGIO = 0x17,
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SIGXCPU = 0x18,
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SIGXFSZ = 0x19,
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SIGVTALRM = 0x1a,
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SIGPROF = 0x1b,
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SIGWINCH = 0x1c,
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SIGINFO = 0x1d,
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SIGUSR1 = 0x1e,
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SIGUSR2 = 0x1f,
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FPE_INTDIV = 0x7,
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FPE_INTOVF = 0x8,
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FPE_FLTDIV = 0x1,
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FPE_FLTOVF = 0x2,
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FPE_FLTUND = 0x3,
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FPE_FLTRES = 0x4,
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FPE_FLTINV = 0x5,
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FPE_FLTSUB = 0x6,
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BUS_ADRALN = 0x1,
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BUS_ADRERR = 0x2,
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BUS_OBJERR = 0x3,
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SEGV_MAPERR = 0x1,
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SEGV_ACCERR = 0x2,
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ITIMER_REAL = 0x0,
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ITIMER_VIRTUAL = 0x1,
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ITIMER_PROF = 0x2,
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EV_ADD = 0x1,
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EV_DELETE = 0x2,
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EV_CLEAR = 0x20,
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EV_RECEIPT = 0x40,
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EV_ERROR = 0x4000,
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EVFILT_READ = -0x1,
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EVFILT_WRITE = -0x2,
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};
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typedef struct MachBody MachBody;
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typedef struct MachHeader MachHeader;
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typedef struct MachNDR MachNDR;
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typedef struct MachPort MachPort;
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typedef struct StackT StackT;
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typedef struct Sigaction Sigaction;
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typedef struct Siginfo Siginfo;
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typedef struct Timeval Timeval;
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typedef struct Itimerval Itimerval;
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typedef struct Timespec Timespec;
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typedef struct FPControl FPControl;
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typedef struct FPStatus FPStatus;
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typedef struct RegMMST RegMMST;
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typedef struct RegXMM RegXMM;
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typedef struct Regs64 Regs64;
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typedef struct FloatState64 FloatState64;
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typedef struct ExceptionState64 ExceptionState64;
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typedef struct Mcontext64 Mcontext64;
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typedef struct Regs32 Regs32;
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typedef struct FloatState32 FloatState32;
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typedef struct ExceptionState32 ExceptionState32;
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typedef struct Mcontext32 Mcontext32;
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typedef struct Ucontext Ucontext;
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typedef struct Kevent Kevent;
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#pragma pack on
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struct MachBody {
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uint32 msgh_descriptor_count;
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};
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struct MachHeader {
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uint32 msgh_bits;
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uint32 msgh_size;
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uint32 msgh_remote_port;
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uint32 msgh_local_port;
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uint32 msgh_reserved;
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int32 msgh_id;
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};
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struct MachNDR {
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uint8 mig_vers;
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uint8 if_vers;
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uint8 reserved1;
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uint8 mig_encoding;
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uint8 int_rep;
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uint8 char_rep;
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uint8 float_rep;
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uint8 reserved2;
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};
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struct MachPort {
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uint32 name;
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uint32 pad1;
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uint16 pad2;
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uint8 disposition;
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uint8 type;
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};
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struct StackT {
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byte *ss_sp;
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uint64 ss_size;
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int32 ss_flags;
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byte Pad_cgo_0[4];
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};
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typedef byte Sighandler[8];
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struct Sigaction {
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byte __sigaction_u[8];
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void *sa_tramp;
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uint32 sa_mask;
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int32 sa_flags;
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};
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typedef byte Sigval[8];
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struct Siginfo {
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int32 si_signo;
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int32 si_errno;
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int32 si_code;
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int32 si_pid;
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uint32 si_uid;
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int32 si_status;
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byte *si_addr;
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byte si_value[8];
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int64 si_band;
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uint64 __pad[7];
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};
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struct Timeval {
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int64 tv_sec;
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int32 tv_usec;
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byte Pad_cgo_0[4];
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};
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struct Itimerval {
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Timeval it_interval;
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Timeval it_value;
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};
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struct Timespec {
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int64 tv_sec;
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int64 tv_nsec;
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};
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struct FPControl {
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byte Pad_cgo_0[2];
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};
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struct FPStatus {
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byte Pad_cgo_0[2];
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};
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struct RegMMST {
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int8 mmst_reg[10];
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int8 mmst_rsrv[6];
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};
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struct RegXMM {
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int8 xmm_reg[16];
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};
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2011-11-10 17:08:28 -07:00
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struct Regs64 {
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uint64 rax;
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uint64 rbx;
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uint64 rcx;
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uint64 rdx;
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uint64 rdi;
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uint64 rsi;
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uint64 rbp;
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uint64 rsp;
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uint64 r8;
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uint64 r9;
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uint64 r10;
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uint64 r11;
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uint64 r12;
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uint64 r13;
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uint64 r14;
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uint64 r15;
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uint64 rip;
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uint64 rflags;
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uint64 cs;
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uint64 fs;
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uint64 gs;
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};
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struct FloatState64 {
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int32 fpu_reserved[2];
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FPControl fpu_fcw;
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FPStatus fpu_fsw;
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uint8 fpu_ftw;
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uint8 fpu_rsrv1;
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uint16 fpu_fop;
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uint32 fpu_ip;
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uint16 fpu_cs;
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uint16 fpu_rsrv2;
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uint32 fpu_dp;
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uint16 fpu_ds;
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uint16 fpu_rsrv3;
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uint32 fpu_mxcsr;
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uint32 fpu_mxcsrmask;
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RegMMST fpu_stmm0;
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RegMMST fpu_stmm1;
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RegMMST fpu_stmm2;
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RegMMST fpu_stmm3;
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RegMMST fpu_stmm4;
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RegMMST fpu_stmm5;
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RegMMST fpu_stmm6;
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RegMMST fpu_stmm7;
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RegXMM fpu_xmm0;
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RegXMM fpu_xmm1;
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RegXMM fpu_xmm2;
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RegXMM fpu_xmm3;
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RegXMM fpu_xmm4;
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RegXMM fpu_xmm5;
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RegXMM fpu_xmm6;
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RegXMM fpu_xmm7;
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RegXMM fpu_xmm8;
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RegXMM fpu_xmm9;
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RegXMM fpu_xmm10;
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RegXMM fpu_xmm11;
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RegXMM fpu_xmm12;
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RegXMM fpu_xmm13;
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RegXMM fpu_xmm14;
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RegXMM fpu_xmm15;
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int8 fpu_rsrv4[96];
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int32 fpu_reserved1;
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};
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struct ExceptionState64 {
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uint16 trapno;
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uint16 cpu;
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uint32 err;
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uint64 faultvaddr;
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};
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struct Mcontext64 {
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ExceptionState64 es;
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Regs64 ss;
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FloatState64 fs;
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byte Pad_cgo_0[4];
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};
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struct Regs32 {
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uint32 eax;
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uint32 ebx;
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uint32 ecx;
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uint32 edx;
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uint32 edi;
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uint32 esi;
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uint32 ebp;
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uint32 esp;
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uint32 ss;
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uint32 eflags;
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uint32 eip;
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uint32 cs;
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uint32 ds;
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uint32 es;
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uint32 fs;
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uint32 gs;
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};
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struct FloatState32 {
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int32 fpu_reserved[2];
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FPControl fpu_fcw;
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FPStatus fpu_fsw;
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uint8 fpu_ftw;
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uint8 fpu_rsrv1;
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uint16 fpu_fop;
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uint32 fpu_ip;
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uint16 fpu_cs;
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uint16 fpu_rsrv2;
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uint32 fpu_dp;
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uint16 fpu_ds;
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uint16 fpu_rsrv3;
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uint32 fpu_mxcsr;
|
|
|
|
uint32 fpu_mxcsrmask;
|
|
|
|
RegMMST fpu_stmm0;
|
|
|
|
RegMMST fpu_stmm1;
|
|
|
|
RegMMST fpu_stmm2;
|
|
|
|
RegMMST fpu_stmm3;
|
|
|
|
RegMMST fpu_stmm4;
|
|
|
|
RegMMST fpu_stmm5;
|
|
|
|
RegMMST fpu_stmm6;
|
|
|
|
RegMMST fpu_stmm7;
|
|
|
|
RegXMM fpu_xmm0;
|
|
|
|
RegXMM fpu_xmm1;
|
|
|
|
RegXMM fpu_xmm2;
|
|
|
|
RegXMM fpu_xmm3;
|
|
|
|
RegXMM fpu_xmm4;
|
|
|
|
RegXMM fpu_xmm5;
|
|
|
|
RegXMM fpu_xmm6;
|
|
|
|
RegXMM fpu_xmm7;
|
|
|
|
int8 fpu_rsrv4[224];
|
|
|
|
int32 fpu_reserved1;
|
|
|
|
};
|
|
|
|
struct ExceptionState32 {
|
2012-01-10 10:48:10 -07:00
|
|
|
uint16 trapno;
|
|
|
|
uint16 cpu;
|
2011-11-10 17:08:28 -07:00
|
|
|
uint32 err;
|
|
|
|
uint32 faultvaddr;
|
|
|
|
};
|
|
|
|
struct Mcontext32 {
|
|
|
|
ExceptionState32 es;
|
|
|
|
Regs32 ss;
|
|
|
|
FloatState32 fs;
|
2009-03-24 14:51:48 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
struct Ucontext {
|
2011-11-10 17:08:28 -07:00
|
|
|
int32 uc_onstack;
|
|
|
|
uint32 uc_sigmask;
|
|
|
|
StackT uc_stack;
|
|
|
|
Ucontext *uc_link;
|
|
|
|
uint64 uc_mcsize;
|
|
|
|
Mcontext64 *uc_mcontext;
|
2009-03-24 14:51:48 -06:00
|
|
|
};
|
2011-11-10 17:08:28 -07:00
|
|
|
|
2013-03-14 00:38:37 -06:00
|
|
|
struct Kevent {
|
|
|
|
uint64 ident;
|
|
|
|
int16 filter;
|
|
|
|
uint16 flags;
|
|
|
|
uint32 fflags;
|
|
|
|
int64 data;
|
|
|
|
byte *udata;
|
|
|
|
};
|
|
|
|
|
2011-11-10 17:08:28 -07:00
|
|
|
|
2009-03-24 14:51:48 -06:00
|
|
|
#pragma pack off
|